3.7.2. Multiplexed trace port signals

This mode of operation multiplexes two trace data signals onto a single trace output pin. This means that the TPA must capture the data on both edges of TRACECLK. This scheme is only recommended for low-frequency designs (for example, less than 50MHz). This is because it is difficult to maintain the required setup and hold between TRACECLK and the trace data signals to the TPA.Half-rate clocking is not supported in this mode, because it already relies on the TPA capturing the state of the trace data pins twice per trace clock cycle.

The ETM Specification provides the trace connector pinout for this mode of operation.

You must pair up the trace signals as shown in Table 3.5. Each row contains a separate pair of signals, one signal occurs on the rising edge of TRACECLK and the other on the falling edge. The PIPESTAT and TRACEPKT[0] signals are sampled first by the TPA to determine the trigger and trace storage qualification information.

Table 3.5. Paired signals in a multiplexed trace port connector

Connector groupsSignals sampled on the rising edge of TRACECLKSignals sampled on the falling edge of TRACECLK
These signals are paired for an 4-pin trace port connectorThese pins are paired for a 6-pin trace port connectorPIPESTAT[0]TRACESYNC
PIPESTAT[1]TRACEPKT[1]
PIPESTAT[2]TRACEPKT[2]
TRACEPKT[0]TRACEPKT[3]
 TRACEPKT[4]TRACEPKT[5]
TRACEPKT[6]TRACEPKT[7]
 TRACEPKT[8]TRACEPKT[9]
TRACEPKT[10]TRACEPKT[11]
TRACEPKT[12]TRACEPKT[13]
TRACEPKT[14]TRACEPKT[15]

Figure 3.16 shows the logic to implement multiplexed data trace signals.

Figure 3.16. Multiplexing data trace signals

Figure 3.17 shows the timing of the multiplexed signals.

Figure 3.17. Multiplexed signal timing

Sufficient delays must be present in the switching of the trace data pins with respect to both edges of TRACECLK. You can achieve this by ensuring that TRACECLK is taken from the root of the ASIC clock tree. It is recommended that you carry out careful analysis to verify the timing on the pins of the ASIC.

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