4.1. About the memory map decode interface

When you implement an ASIC or ASSP, there are usually a number of memory mapped peripherals and areas of external and internal RAM, ROM, and flash, for example.

The memory map decode outputs allow simple, low-cost decoding of this address map using ASIC-specific logic. This logic drives the MMDIN inputs to the ETM, making them available to you as ETM resources, in a similar way to the address comparator and address range comparator resources.

The structure of the Memory Map Decode (MMD) logic is shown in Figure 4‑1

Figure 4.1. Memory map decode logic structure

In Figure 4.1, MMD Address signals are:

All unused MMDIN inputs must be tied to logic zero.The MMDCTRL bus comes from an ETM register, programmed by the Trace debug tools. These allow you to specify the value to be programmed into this 8-bit register.

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