This scheme is recommended in systems that reuse general ASIC pins for trace, or for high-speed systems where the switching frequency of the off-chip trace signals is unacceptable. Figure 3.18 shows logic to implement a demultiplexed trace port.

Figure 3.19 shows the timings for demultiplexed trace data signals.

Half-rate clocking can be supported with demultiplexed trace data signals. However, you must take care to produce a clean trace clock. The following Verilog is an example of how a half-rate clock (in effect one quarter of the rate of the ETM clock) might be produced:

always @(posedge CLK or negedge nRESET)  if (nRESET == 1'b0)    begin      State <= 2'b00;      HalfTraceClk <= 1'b0;    end  else    case (State[1:0])      2'b00  : begin State <= 2'b01; HalfTraceClk <= 1'b0; end      2'b01  : begin State <= 2'b10; HalfTraceClk <= 1'b0; end      2'b10  : begin State <= 2'b11; HalfTraceClk <= 1'b1; end      2'b11  : begin State <= 2'b00; HalfTraceClk <= 1'b1; end      default : begin State <= 2'bXX; HalfTraceClk <= 1'bX; end

This scheme ensures that the delay from the system clock to TRACECLK is minimized and ensures that there are no registers clocked from the data output of other registers. This helps static timing analysis.

In demultiplexed mode, the TPA must examine the two cycles of trace data in parallel to determine whether a trigger has occurred. It must also check for the trace disabled pipeline status in both cycles of data.