3.2.4. Coprocessor data bus connections

Figure 3.1 shows the coprocessor data bus connections for a unidirectional bus based system having an ETM7 and an ARM7TDMI-S or ARM7TDMI core.

Figure 3.1. Coprocessor unidirectional data bus connections

The logic that drives asel, bsel, and csel from the relevant ARM7TDMI or ARM7TDMI pins is:

	assign asel = ~(cprt | (cpdt & nRW_r));	assign bsel = ~cpdt;	assign csel = cprt;	assign cpdt = ~nMREQ_r & ~CPA_r2 & nOPC_r;	assign cprt = nMREQ_r & SEQ_r;

Note

cpdt shows that the current cycle is a load or store cycle due to an LDC or STC instruction.cprt shows that the current cycle is a coprocessor register transfer cycle.

The other signals used to derive these terms are as follows.The ARM7TDMI-S register logic is:

always @(posedge CLK)	if (CLKEN)		begin			nMREQ_r <= CPnMREQ; //Output from ARM7TDMI-S			SEQ_r   <= CPSEQ; // Output from ARM7TDMI-S			nOPC_r  <= CPnOPC; // Output from ARM7TDMI-S			nRW_r   <= WRITE; // Output from ARM7TDMI-S			CPA_r   <= CPA; // Input to ARM7TDMI-S			CPA_r2  <= CPA_r;		end

The ARM7TDMI register logic is similar, but requires that the CPA input to ARM7TDMI is registered half a cycle later than ARM7TDMI-S:

always @(negedge MCLK)	if (nWAIT)		begin			nMREQ_r <= nMREQ; // Output from ARM7TDMI			SEQ_r   <= SEQ;   // Output from ARM7TDMI			nOPC_r  <= nOPC;  // Output from ARM7TDMI			nRW_r   <= nRW;   // Output from ARM7TDMI			CPA_r2  <= CPA_r;		end
always @(posedge MCLK)	if (nWAIT)		CPA_r   <= CPA;     // Input to ARM7TDMI

Figure 3.2 shows the coprocessor data bus connections for a bidirectional bus based system having an ETM7 and an ARM7TDMI core.

Figure 3.2. Coprocessor bidirectional data bus connections

To ensure that tracing of coprocessor instructions functions correctly it is essential that:

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