7.3.1. Dedicated trace port

This is the preferred implementation for connecting a TPA to a trace port. The TPA is the only load on the nodes connected to target ASIC pins, so the only factor affecting operation is signal integrity at the TPA connector.

If you know the characteristics of your PCB tracks, use the actual trace impedance and propagation delay. If you do not have access to this information, use the following guidelines for microstrip (track on outer layer over a ground plane) on FR4 PCB:

To design the target system effectively, you must know:

If you do not know the characteristics of the signals from your ASIC, consult your ASIC vendor. It is difficult to provide any general rule because ETM output drivers and timings vary between ASIC vendors.

PCB track length

You must match all TRACECLK, PIPESTAT[2:0], TRACESYNC, and TRACEPKT[15:0] track lengths between the ASIC and the trace port connector within 100ps. Overall differences in track lengths directly impact setup and hold requirements as follows:

  • if the clock is delayed compared to the data, you must increase the setup specification by the additional clock delay

  • if any data is delayed compared to the clock, you must add the delay to the setup requirement

  • if data paths are such that data has both greater than and less than delays compared with the clock, you must add the difference to both the setup and hold specification.

Signal quality

The primary variable that characterizes signal quality is the rise time of a signal compared to its propagation time. It is this relationship that affects the track length, and this is where the minimum signal rise and fall time becomes important.

To ensure accurate data acquisition, you must minimize all reflections, overshoot, and undershoot. Aim to keep the one-way propagation time for all tracks at less than one third of the signal rise time.

As the fabrication process for your ASIC improves, your output driver is likely to improve and your rise and fall times are likely to decrease. If you cannot keep the propagation time for all tracks below one third of the signal rise time, some form of signal termination is required. This can be either of the following:

Series termination

(Recommended method.) The series resistor must be placed as close as possible to the ASIC pin (half an inch or closer). The value of this series resistor plus the output impedance of the signal driver must closely match the impedance of the PCB track.

Parallel or matched AC termination

If you cannot use series termination, add parallel or matched AC termination on each signal track at the TPA target header. This requires significantly more power from the ASIC, and the AC termination must closely match the frequency and rise time of the terminated signal. In practice therefore, parallel termination is rarely possible.

If the total track length is one rise time propagation delay or greater in length, follow standard high-speed design practices to minimize cross talk between the clock and the data signals. (The total track length is the target PCB track length plus any PCB track on the TPA buffer board.)

Note

ASIC output pads with an output impedance that is matched to the PCB track might be available from your ASIC vendor. If these are used, the signal quality of the trace port signals is significantly improved.

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