5.2. Release package structure

The ASIC trace validation package comprises:

Validation package

This is assigned the ARM part numbers TM020-SW-01001 and TM030-SW-01001. The contents of the packages are identical. Each package contains:

  • ARM assembler source of the example test program, including an example Verilog test bench to run it on

  • decompression and comparison scripts.

Boundary Scan Trickbox (BST)

This is a ModelGen Design Signoff Model (DSM) that drives the JTAG interface of the ASIC. It is controlled by commands written in a file called JTAGbsi. The format of these commands is hard to write manually, and therefore a script called parse_bsi.pl is also provided in the BST release and in the scripts directory. This script allows higher level commands, which can include ARM assembler instructions, to be written and turned into the low-level commands understood by the BST.

ARM7TDMI model

This is a ModelGen DSM that is used in the example Verilog test bench. It contains example components of a typical ARM7TDMI-based ASIC design.


There is no ETM7-specific validation package. All tools and examples are common to ETM7 and ETM9.

Details of the BST and scripts are provided in the simulator-specific BST release deliverable, including how the BST is integrated into the simulator being used.


The parse_bsi.pl script requires that the ARM toolkit is available. This is used to assemble the ARM instructions that are scanned into the ARM processor when it is in debug state.

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