The verilog file, SimpleSystem.v, is in the verilog/tbench directory. This instances an ARM7TDMI, ETM7, and the BST, and provides a simple platform for you to try out the example test program.

You are advised to run the test bench as supplied to gain an insight into the operation of a typical system. You can then modify the test bench to match your own system configuration (see Modifying your ASIC test bench), before using the modified test bench for testing.

To compile and run the test bench for the ModelSim verilog simulator, use the following command in the AsicValKit directory:

	ln -s hex/example1.hex rom.hex

	ln -s bsi/example1.bsi JTAGbsi

This links in the files that the test bench looks for. They are provided as precompiled object files. Before you compile the verilog, you must edit the paths to the DSMs in the dotcshrc file and the verilog/tbench/verilog.vc file. For example, in dotcshrc:

setenv DIR_ARM7TDMIr3 .../arm7tdmi_vsystemv_SunOS5_3A.00/ARM7TDMIr3

and, in verilog.vc:

-v .../arm7tdmi_vsystemv_SunOS5_3A.00/ARM7TDMIr3/ARM7TDMIr3.v

The next step is to compile and run the test bench verilog. For example, if you are using ModelSim:

	vlib work

	vlog -f verilog.vc verilog/tbench/SimpleSystem.v

	vsim -i SimpleSystem

For Verilog-XL, use the following:

	verilog -f verilog.vc verilog/tbench/SimpleSystem.v