3.3.2. ETM reset

nRESET resets all of the ETM7 state, with the exception of the ETM control register, and flushes the trace FIFO. You can connect nRESET to the same reset as the processor. However, this prevents trace being used during a warm reset of the ARM7. ARM strongly recommends that you use the TAP reset (nTRST/DBGnTRST) to reset the ETM7 state.

In systems where CLK and TCK are asynchronous, nTRST needs to be synchronized to CLK. You can do this using the arrangement shown in Figure 3.5.

Figure 3.5. Synchronizing reset

Synchronizing nTRST to CLK allows nTRST to reset the ETM even when CLK is running slowly, or is stopped.

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