3.5.3. FIFOFULL

This signal changes on the rising edge of CLK and is active HIGH. When asserted it indicates that:

You can use FIFOFULL to stall the ARM core, so that more trace data is not generated until the FIFO has drained. It is recommended that you implement this by controlling the CLKEN input to the ARM core, rather than gating the clock. If the clock is gated there is a risk of system lock-up, because stopping the clock prevents the FIFO from draining, and prevents FIFOFULL from being de-asserted.

If CLKEN is supported you can increase the accuracy of the tracing by slowing down the processor when the trace port bandwidth is exceeded. This allows you to slow down non real-time areas of code while critical regions remain unaffected. The Embedded Trace Macrocell Specification describes how this is achieved in more detail. Briefly however, you specify, within the ETM, the address regions in which FIFOFULL can be asserted.

If the system designer is not able to support the use of this signal no harm results, even if the FIFOFULL logic inside the ETM is programmed and enabled, because the logic does not have any direct effect on the behavior of the ETM. However, if FIFOFULL is not used, there is a risk of some trace data being lost while the FIFO drains.

Note

To maintain interrupt response time in the system, you might have to override FIFOFULL assertion when nIRQ and/or nFIQ are asserted.

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