3.5.2. Using the PWRDOWN output

The ETM7 provides an output called PWRDOWN. When HIGH this indicates that the ETM is not currently enabled, so you can stop the CLK input and hold the other ETM7 signals stable. You can use this to reduce system power consumption when trace is not being used. When a TAP reset (nTRST) occurs, PWRDOWN is automatically forced HIGH until the ETM7 control register has been programmed. You can use the PWRDOWN output directly to gate the ETM7 CLK input. This is shown in Figure 3.12.

Figure 3.12. Clock gating the ETM7

The PWRDOWN output is controlled by the ARM debug tools, and is automatically cleared at the start of a debug session.

Some ARM macrocells implement this logic internally by providing an ETMPWRDOWN input to the trace interface, causing the clock and data outputs to the ETM to be stopped. Refer to the Technical Reference Manual of the applicable core for further details.

The PWRDOWN signal is changed synchronously to TCK. Because PWRDOWN changes many cycles before trace is enabled, this does not cause any metastability problems if you use PWRDOWN to gate the ETM7 clock. If using PWRDOWN in this way causes problems with static timing analysis, you can synchronize PWRDOWN to CLK before using it to gate the ETM7 clock.

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