3.6.3. Dual-processor tracing

Where there are multiple ARM processors on a single chip, it is recommended that each ARM processor has its own dedicated ETM.

The principle of controlling the port width, described in Single-processor tracing, can be extended to support dual-processor systems without dedicating a large number of pins to the trace signals.

The recommended dual trace configuration uses 21 pins on the ASIC, because this matches the 20 data pins and 1 clock pin defined in the trace connector specification. These pins are configured as 20 data pins and a single clock pin (assuming that both processors are clocked off a single clock).

This allows a number of configurations. Possible configurations for a single processor are shown in Table 3.3.

Table 3.3. Single-processor configurations

TRACEPKT

PIPESTAT

TRACESYNC

Total

16 trace packet

3 status

1 sync

20 data pins

8 trace packet

3 status

1 sync

12 data pins

4 trace packet

3 status

1 sync

8 data pins

You can, therefore, set a single trace port to allow the configurations shown in Table 3.4.

Table 3.4. Dual-processor trace port configurations

Processor A

Processor B

20 data

No trace

12 data

8 data

8 data

12 data

No trace

20 data

Pseudo-HDL to implement this is as follows:

if (PORTSIZE_B = 21)
	TRACE_DATA <= {PIPESTAT_B, TRACESYNC_B, TRACEPKT_B[15:0]}
else 	if (PORTSIZE_A = 13) and (PORTSIZE_B = 9)
	TRACE_DATA <= {PIPESTAT_B, TRACESYNC_B, TRACEPKT_B[3:0],
					PIPESTAT_A, TRACESYNC_A, TRACEPKT_A[7:0]}
else 	if (PORTSIZE_A = 9) and (PORTSIZE_B = 13)
	TRACE_DATA <=			 {PIPESTAT_A, TRACESYNC_A, TRACEPKT_A[3:0],
					PIPESTAT_B, TRACESYNC_B, TRACEPKT_B[7:0]}
else
	-- select A as the "master" for all other combinations. 
	TRACE_DATA <= {PIPESTAT_A, TRACESYNC_A, TRACEPKT_A[15:0]}
end if

The Embedded Trace Macrocell Specification documents the target system connector pin allocations for single and dual-processor configurations. Support for the dual-processor pinouts is dependent on the debug tools and the TPA.

It is not recommended that you connect a single ETM7 to multiple ARM7 processors, because there is no general mechanism available to control the logic that selects which processor is connected to the single ETM.

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