3.6.4. Trace signal output timing

The trace connection to the TPA requires a clock, TRACECLK, to be exported from the ASIC. This is not generated by the ETM7, but must be generated by the system implementer. It is essential that you balance the clock to provide sufficient hold time on the trace data signals. The required hold times are defined in the Embedded Trace Macrocell Specification. It is essential that you maintain these hold times to guarantee reliable trace functionality.

It is recommended that the trace data signals are shifted by a clock phase from TRACECLK. This ensures that, on TRACECLK transitions, the trace data signals are stable, with a sufficient setup and hold time around the clock edge. Most TPAs require approximately 3ns of data valid time, and a hold time in the range 1 to 2ns, or greater, for reliable acquisition.

The ETM also supports a half-rate clocking mode, controlled by the CLKDIVTWOEN ETM7 output. When asserted, you should drive TRACECLK from the ETM clock (CLK) divided by two. When the debugger selects this mode, it also tells the TPA that it must sample the trace data signals on both edges of the clock, instead of only the rising edge.

Note

You do not have to implement half-rate clocking, and for low-speed systems (for example, less than 50MHz) the normal clocking mode is adequate. The primary purpose of half-rate clocking is to reduce the signal transition rate on the TRACECLK pin of the ASIC. This might be necessary to reduce electrical interference, to maintain TRACECLK signal integrity when using low drive strength pads, or for systems with very high clock speeds.

Figure 3.14 shows an example circuit that implements both half-rate clocking and shifting of the trace data with respect to the clock.

Figure 3.14. Trace output circuit with inverted clock

If your design flow does not allow you to invert the clock, you can also use falling edge D-types to retime the trace data signals, as shown in Figure 3.15.

Figure 3.15. Trace output circuit using falling-edge D-types

It is recommended that you analyze carefully the timing of the trace data and clock signals to ensure the optimum setup and hold timing on the pins of the ASIC. It is also advisable to do detailed simulations of the output pads, package (for example, bond wires), PCB tracking, and logic analyzer loads to ensure the setup and hold times and signal integrity are met for the analyzer.

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