5.7.13. CLKDIVTWOEN

The recommended configuration allows you to use this signal to divide the trace clock, see Trace signal output timing. To control this output, you can use the SET_CLKDIVTWOEN and UNSET_CLKDIVTWOEN macros in the BST sequences. You must do this before starting tracing.

The EtmMonitor block has a CLKDIVTWOEN input which, when set, causes it to sample the trace signals on both edges of the trace clock. You can tie this HIGH when testing half-rate clocking or, if using Verilog, use a direct reference to the ETM output to directly observe the state of the CLKDIVTWOEN signal.

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