Glossary

This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended.

Application Specific Integrated Circuit

An integrated circuit that has been designed to perform a specific application function. It can be custom-built or mass-produced.

Application Specific Standard Part/Product

Another name for an Application Specific Integrated Circuit. The name implies that the device performs complete functions, and can be used as a building block in a range of products.

ASIC

See Application Specific Integrated Circuit.

ASSP

See Application Specific Standard Part/Product.

Clock gating

Gating a clock signal for a macrocell with a control signal (such as PWRDOWN) and using the modified clock that results to control the operating state of the macrocell.

Debugger

A debugging system which includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

Embedded Trace Macrocell

A hardware macrocell which, when connected to a processor core, outputs instruction and data trace information on a trace port.

ETM

See Embedded Trace Macrocell.

Half-rate clocking

Dividing the trace clock by two so that the TPA can sample trace data signals on both the rising and falling edges of the trace clock. The primary purpose of half-rate clocking is to reduce the signal transition rate on the trace clock of an ASIC for very high-speed systems.

Macrocell

A complex logic block with a defined interface and behavior. A typical VLSI system will comprise several macrocells (such as an ARM9E-S, an ETM9, and a memory block) plus application-specific logic.

Joint Test Action Group

The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.

JTAG

See Joint Test Action Group.

SCREG

The currently selected scan chain number in an ARM TAP controller.

SPICE

An accurate transistor-level simulation tool.

TAP

See Test access port.

Test Access Port

The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST.

Trace driver

An RDI target that controls a piece of trace hardware. That is, the trigger macrocell, trace macrocell and trace capture tool.

Trace hardware

A term for a device that contains an Embedded Trace Macrocell.

Trace port

A port on a device, such as a processor or ASIC, which is used to output trace information.

TPA

See Trace Port Analyzer.

Trace Port Analyzer

A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.

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