A.1. Signal descriptions

The ETM7 signal descriptions are listed in Table A.1

Table A.1. ETM7 signals

Type

Signal name

Description

Input

A[31:0]

The processor address bus driven by the ARM.

Input

ABORT

The Abort signal driven into the ARM. The ABORT signal is used to tell the processor that the requested memory access is not allowed.

Input

ARMTDO

The TDO output signal from the ARM, or from an external scan chain.

Input

BIGEND

The signal driving the ARM BIGEND/CFGBIGEND input. When HIGH the processor treats bytes in memory as big-endian format. When LOW memory is treated as little-endian. This is a static configuration signal.

Input

CLK

This clock times all operations in the ETM7. All outputs change from the rising edge and all inputs are sampled on the rising edge. The clock can be stretched in either phase. Synchronous wait states can be added using the CLKEN signal.

Output

CLKDIVTWOEN

If HIGH, indicates that the ETM is in half-rate clocking mode.

Input

CLKEN

The ETM can be stalled by driving CLKEN LOW. This signal should be held HIGH at all other times. This must be the same as the signal that drives the ARM nWAIT/CLKEN input.

Input

CPA

The coprocessor absent signal driven into the ARM.

Input

CPB

The coprocessor busy signal driven into the ARM.

Input

DBGACK

The debug acknowledge signal driven by the ARM. When HIGH this signal indicates that the ARM is in debug state.

Output

DBGRQ

Debug request. A signal that can be used to stop the ARM processor.

Output

ETMEN

This output will be HIGH when the debugger has enabled the ETM.

Input

EXTIN[3:0]

External inputs to the ETM. These inputs are available as resources within the ETM.

Output

EXTOUT[3:0]

External outputs from the ETM. Can be used to trigger hardware inside the ASIC, or external equipment such as a logic analyzer.

Output

FIFOFULL

When enabled, this indicates that there is less than a user-programmed number of bytes in the ETM FIFO.

InputINSTRVALIDThe INSTRVALID pipeline status signal driven by the ARM macrocell. The instruction valid signal indicates that the instruction in the Execute stage is valid, and has not been flushed.

Input

MAS[1:0]

The memory access size bus driven by the ARM. These encode the size of a data memory access in the following cycle.

Output

MMDCTRL[7:0]

A control bus, used to reconfigure the memory map decode logic.

Output

MMDA[31:0]

The ARM A[31:0] signal, pipelined for the memory map decode interface.

Output

MMDMAS[1:0]

The ARM MAS[1:0] signal, pipelined for the memory map decode interface.

OutputMMDIN[15:0]Memory map decode inputs to the ETM trigger logic.

Output

MMDnMREQ

The ARM nMREQ signal, pipelined for the memory map decode interface.

Output

MMDnOPC

The ARM nOPC signal, pipelined for the memory map decode interface.

Output

MMDnRW

The ARM nRW signal, pipelined for the memory map decode interface.

Output

MMDTBIT

The ARM TBIT signal, pipelined for the memory map decode interface.

Input

nCPI

The not coprocessor instruction signal driven into the ARM.

InputnEXECThe nEXEC pipeline status signal driven by the ARM macrocell. The instruction executed signal indicates that the instruction in the Execute stage of the pipeline follower of the ETM7 has been executed.

Input

nMREQ

The memory request signal driven by the ARM. If LOW at the end of a cycle then the processor requires a memory access in the following cycle.

Input

nOPC

The not coprocessor opcode signal driven into the ARM.

Input

nRESET

Active LOW ETM reset.

Input

nRW

The read write signal driven by the ARM. If LOW at the end of a cycle then any memory access in the following cycle is a read. If HIGH then it is a write.

Input

nTRST

Active LOW JTAG test reset.

Output

PIPESTAT[2:0]

Indicates the pipeline status of the ARM.

OutputPORTMODE[1:0]This output bus allows the on-chip trace port output logic to be configured for normal, multiplexed, or demultiplexed modes of operation.

Output

PORTSIZE[2:0]

Indicates the currently selected port size in use on the TRACEPKT[15:0] bus.

InputPROCID[31:0]This bus provides a copy of the current process ID or overlay number from the ARM system control coprocessor or peripheral.
InputPROCIDWRThis signal must be asserted whenever the PROCID bus changes. This causes the ETM to output the new process ID at the next available opportunity.

Output

PWRDOWN

When HIGH, indicates that the ETM may be powered down.

Input

Input

RANGEOUT0,

RANGEOUT1

The RANGEOUT0,1/DBGRNG[1:0] EmbeddedICE signals driven by the ARM. The EmbeddedICE RANGEOUT signals indicate that the corresponding watchpoint unit has matched the conditions currently present on the address, control and data buses. These signals are independent of the state of the enable control bit of the watchpoint unit.

Input

RDATA[31:0]

The DIN/RDATA bus driven into the ARM.

Input

SEQ

The data sequential address signal driven by the ARM. If HIGH at the end of the cycle then any data memory access in the following cycle is sequential from the last memory access.

InputSYSOPT[7:0]Indicates to the debug tools the system options that have been implemented. Bits are tied HIGH or LOW as appropriate, as part of the integration process.

Input

TBIT

The TBIT signal driven by the ARM. When HIGH denotes that the ARM processor is in Thumb state. When LOW the processor is in ARM state. This signal is valid with the address.

Input

TCK

Test clock.

Input

TCKEN

Synchronous enable for test clock.

Input

TDI

Test data input.

Output

TDO

Test data output.

Input

TMS

Test mode select.

Output

TRACEPKT[15:0]

The trace packet port.

Output

TRACESYNC

A synchronization signal, indicating the start of a branch sequence on the trace packet port.

Input

WDATA[31:0]

The DOUT/WDATA bus driven by the ARM.

Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DDI 0158D
Non-Confidential