ARM PrimeCell ™ SDRAMController (PL170) Technical Reference Manual


List of Tables

3.1. PrimeCell SDRAM register summary
3.2. Configuration register 0
3.3. Configuration register 1
3.4. Control bits for memory device initialization
3.5. Refresh timer register
3.6. Write buffer time-out register
3.7. Chip select address decoder truth table
3.8. 16M SDRAM (1Mx16) T=0, B=0, F=0, X=0, use 11 as bank select
3.9. 16M SDRAM (2Mx8) T=1, B=0, F=0, X=0, use 11 as bank select
3.10. 64M SDRAM (2Mx32, 4Mx16) T=0, B=1, F = 0, X=0, use 12 and13 as bank selects
3.11. 64M SDRAM (8Mx8) T=1, B=1, F=0, X=0, use 12 and 13 as bankselects
3.12. 128M SDRAM (16Mx8) T=1, B=1, F=0, X=0, use 12 and 13 as bankselects
3.13. 128M SDRAM (8Mx16, 4Mx32) T=0, B=1, F=0, X=0, use 12 and13 as bank selects
3.14. 256M SDRAM (16Mx16,) T=0, B=1, F=1, X=0, use 13 and 14 asbank selects
3.15. 256M SDRAM (32Mx8) T=1, B=1, F=1, X=0, use 13 and 14 as bankselects
3.16. 16M SDRAM (1Mx16) T=0, B=0, F=0, X=1, use 11 as bank select
3.17. 16M SDRAM (2Mx8) T=1, B=0, F=0, X=1, use 11 as bank select
3.18. 64M SDRAM (2Mx32, 4Mx16) T=0, B=1, F = 0, X=1, use 12 and13 as bank selects
3.19. 64M SDRAM (8Mx8) T=1, B=1, F=0, X=1, use 12 and 13 as bankselects
3.20. 128M SDRAM (16Mx8) T=1, B=1, F=0, X=1, use 12 and 13 as bankselects
3.21. 128M SDRAM (8Mx16) T=0, B=1, F=0, X=1, use 12 and 13 as bankselects
3.22. 256M SDRAM (16Mx16) T=0, B=1, F=1, X=1, use 13 and 14 asbank selects
3.23. 256M SDRAM (32Mx8) T=1, B=1, F=1, X=1, use 13 and 14 as bankselects
A.1. AMBA AHB signals
A.2. Miscellaneous signals
A.3. Off-chip signals
B.1. Commands

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Revision History
Revision A 15October 1999 First release
Revision B 22December 1999 Minor changes on pages 1-3, 3-2,3-4, 3-9, 3-10, A-2, A-5, A-6.Minor changes to Figures 2-1 and 2-2.Figure 2-3 added, with supporting text.Table 3-2 revised: new rowadded at end.Tables 3-8 to 3-11 revised: additional column and detailchanges.Tables 3-12 and 3-13 added to show address mapping for 256MSDRAM.
Revision C 18April 2000 Minor changes on pages 1-4, 2-3 andA-6.Minor changes to Figure 2-3.Tables 3-12 and 3-13 added to showaddress mapping for 128M SDRAM.Tables 3-8 to 3-11 rearranged inSDRAM sequence.Table A-2 revised to include BIGENDIAN signal, withsupporting note.Tables 3-8 to 3-15 revised. Tables 3-16 to 3-23added.
Revision D 29June 2001 Configurations revised in Tables 3-13,3-14, 3-18, 3-21, and 3-22.References to AP in Tables 3-8 to 3-23changed to A to conform to configuration register.
Copyright © 1999-2001 ARM Limited. All rights reserved. ARM DDI 0159D
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