PrimeCell™ Color LCD Controller (PL110) Technical Reference Manual 4.3.2. Integration Test Output Register 1, CLCDITOP1

4.3.2. Integration Test Output Register 1, CLCDITOP1

CLCDITOP1 is one of two Integration Test Output Registers. If the CLCDTCR[0] ITEN bit is high then the CLCDITOP1 register value is used, otherwise the functional mode value is driven onto the intra-chip output port. The register bit assignments are listed in Table 4.3.

Table 4.3. CLCDITOP1 bit assignments

Bit	Name	Type	Description
[31:6]	-	-	Reserved, do not modify, write as zero
[5]	CLCDCLKSEL	Read/write	Intra-chip output. Writes specify the value to be driven on the CLCDCLKSEL line when in integration test mode. A read returns the value of the CLCDCLKSEL signal at the output of the test multiplexor.
[4]	CLCDMBEINTR	Read/write	Intra-chip output. Writes specify the value to be driven on the CLCDMBEINTR line when in integration test mode. A read returns the value of the CLCDMBEINTR signal at the output of the test multiplexor.
[3]	CLCDFUFINTR	Read/write	Intra-chip output. Writes specify the value to be driven on the CLCDFUFINTR line when in integration test mode. A read returns the value of the CLCDFUFINTR signal at the output of the test multiplexor.
[2]	CLCDLNBUINTR	Read/write	Intra-chip output. Writes specify the value to be driven on the CLCDLNBUINTR line when in integration test mode. A read returns the value of the CLCDLNBUINTR signal at the output of the test multiplexor.
[1]	CLCDVCOMPINTR	Read/write	Intra-chip output. Writes specify the value to be driven on the CLCDVCOMPINTR line when in integration test mode. A read returns the value of the CLCDVCOMPINTR signal at the output of the test multiplexor.
[0]	CLCDINTR	Read/write	Intra-chip output. Writes specify the value to be driven on the CLCDINTR line when in integration test mode. A read returns the value of the CLCDINTR signal at the output of the test multiplexor.

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