HADDRM[31:0]

Output

AMBA AHB bus

Address bus.

HBURSTM[2:0]

Output

AMBA AHB bus

Indicates if the transfer forms a part of the burst. 4, 8, and 16 incrementing bursts are supported.

HBUSREQM

Output

Arbiter

Bus request. When HIGH this indicates that the bus master requires the bus.

HGRANTM

Input

Arbiter

Bus grant. This signal indicates that the bus master is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADYMin is HIGH, and this master gets access to the bus when both HREADYMin and HGRANTM are HIGH.

HLOCK

Output

Arbiter

When HIGH this signal indicates that the master requires locked access.

HPROT[3:0]

Output

AMBA AHB bus

The protection signals provide additional information about a bus access. They are primarily intended for use by any module that wishes to implement some level of protection.

HRDATAM[31:0]

Input

AMBA AHB bus

Read data bus.

HREADYMin

Input

AMBA AHB bus

When HIGH this signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend the transfer.

HRESPM[1:0]

Input

AMBA AHB bus

The transfer response provides additional information on the status of a transfer. Only OKAY, ERROR, and RETRY responses are fully supported.

HSIZEM[2:0]

Output

AMBA AHB bus

Indicates the size of the transfer. Only word size accesses are supported.

HTRANSM[1:0]

Output

AMBA AHB bus

Indicates the type of the current transfer, which can be nonsequential, sequential, idle or busy.

HWRITEM

Output

AMBA AHB bus

When HIGH this signal indicates a write transfer and when LOW a read transfer.