V_dd is simultaneously applied to the SoC that contains the CLCDC and panel display driver logic. The signals CLLP, CLCP, CLFP, CLAC, CLD[23:0], and CLLE are held LOW.

When V_dd is stabilized, a 1 is written to the LcdEn bit in the LCDControl Register. This puts the signals CLLP, CLCP, CLFP, CLAC, and CLLE into their active states but the CLD[23:0] signals remain LOW.

When the signals in Step 2 have stabilized, where appropriate, the contrast voltage V_ee (this is not controlled or supplied by the CLCDC) is then applied.

You can use a software timer routine, if required, to provide the minimum display specific delay time between application of the control signals and power to the panel display. On completion of the software timer routine, power is applied to the panel by writing a 1 to the LcdPwr bit within the LcdControl Register which, in turn, sets the CLPOWER signal HIGH and puts the CLD[23:0] signals into their active state. The CLPOWER signal is expected to be used to gate the power to the LCD panel.