PrimeCell ™ Color LCDController (PL110) Technical Reference Manual

Revision:r1p2


Table of Contents

Preface
About this document
Intended audience
Organization
Product revision status
Typographical conventions
Other conventions
Further reading
Feedback
Feedback on this document
Feedback on the ARM PrimeCell CLCDC(PL110)
1. Introduction
1.1. About the ARM PrimeCell Color LCD Controller(PL110)
1.1.1. Features of the PrimeCell Color LCD Controller
1.1.2. Programmable parameters
1.1.3. Target markets
1.1.4. LCD panel resolution
1.1.5. Types of LCD panel supported
1.1.6. Number of colors supported
1.1.7. LCD powering up and powering down sequencesupport
1.2. Product history
2. Functional Overview
2.1. ARM PrimeCell Color LCD Controller(PL110) overview
2.2. AMBA AHB interface
2.2.1. AMBA AHB slave interface
2.2.2. AMBA AHB master interface
2.2.3. Dual DMA FIFOs and associated control logic
2.2.4. Pixel serializer
2.2.5. RAM palette
2.2.6. Gray scaler
2.2.7. Upper and lower panel formatters
2.2.8. Panel clock generator
2.2.9. Timing controller
2.2.10. Interrupt generation
2.2.11. Bus architecture
3. Programmer’s Model
3.1. Summary of registers
3.2. Register descriptions
3.2.1. Horizontal Axis Panel Control Register,LCDTiming0
3.2.2. Vertical Axis Panel Control Register,LCDTiming1
3.2.3. Clock and Signal Polarity Control Register,LCDTiming2
3.2.4. Line End Control Register, LCDTiming3
3.2.5. Upper and Lower Panel Frame Base AddressRegisters, LCDUPBASE and LCDLPBASE
3.2.6. Interrupt Mask Set/Clear Register,LCDIMSC
3.2.7. Control Register, LCDControl
3.2.8. Raw Interrupt Status Register, LCDRIS
3.2.9. Masked Interrupt Status Register, LCDMIS
3.2.10. Interrupt Clear Register, LCDICR
3.2.11. Upper and Lower Panel Current AddressValue Registers LCDUPCURR and LCDLPCURR
3.2.12. Color Palette Register, LCDPalette
3.2.13. Peripheral Identification Registers,CLCDPERIPHID0-3
3.2.14. PrimeCell Identification Registers,CLCDPCELLIDID0-3
3.3. Interrupts
3.3.1. CLCDMBEINTR
3.3.2. CLCDVCOMPINTR
3.3.3. CLCDLNBUINTR
3.3.4. CLCDFUFINTR
4. Programmer’s Model for Test
4.1. Scan testing
4.2. Summary of test registers
4.3. Test register descriptions
4.3.1. Test Control Register, CLCDTCR
4.3.2. Integration Test Output Register 1,CLCDITOP1
4.3.3. Integration Test Output Register 2,CLCDITOP2
A. Signal Descriptions
A.1. AMBA AHB Slave interface signals
A.2. AMBA AHB Master interface signals
A.3. External pad interface signals
A.4. On-chip signals
A.5. Scan test signals
A.6. LCD panel signal multiplexing details

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksof ARM Limited in the EU and other countries, except as otherwisestated below in this proprietary notice. Other brands and names mentionedherein may be the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A August1999 First release
Revision B 26August 1999 Minor corrections to Chapter 4. Changesto Appendix A, Tables A-5 and A-6 added.
Revision C 8September 1999 Figs 2-3 to Fig 2-8 inserted. Changesto Tables A-5 and A-6.
Revision D 1December 2000 Errata changes to Fig 2-6, Table3-2, 3-9, 3-14, and A-5. Section 1.1.6 and Fig 1-1 added.
Revision E 9May 2003 Update to r1p2. Conversion to SGML.
Copyright © 1999-2003 ARM Limited. All rights reserved. ARM DDI 0161E
Non-Confidential