2.3.5. Register 15: Test

This register provides access to the tightly-coupled instruction and data SRAM test features supported by the ARM966E-S. The register map for CP15 register 15 is shown in Table 2.4.

Table 2.4. Register 15: Test register map

Register

Read

Write

BIST control register

MRC p15, 1, Rd, c15, c0, 1

MCR p15, 1, Rd, c15, c0, 1

Instruction BIST address register

MRC p15, 1, Rd, c15, c0, 2

MCR p15, 1, Rd, c15, c0, 2

Instruction BIST general register

MRC p15, 1, Rd, c15, c0, 3

MCR p15, 1, Rd, c15, c0, 3

Data BIST address register

MRC p15, 1, Rd, c15, c0, 6

MCR p15, 1, Rd, c15, c0, 6

Data BIST general register

MRC p15, 1, Rd, c15, c0, 7

MCR p15, 1, Rd, c15, c0, 7

Note

Opcode_1 is set HIGH when accessing Register 15. Opcode_2 is used to index registers within the Register 15 register map.

BIST control register

Table 2.5 shows the bit assignments within the BIST control register.

Table 2.5. BIST control register

Register bit

Meaning when written

Meaning when read

31:21

Instruction SRAM BIST size

Instruction SRAM BIST size

20

Reserved (should be zero)

Instruction SRAM BIST complete flag

19

Reserved (should be zero)

Instruction SRAM BIST fail flag

18

Instruction SRAM BIST enable

Instruction SRAM BIST enable

17

Instruction SRAM BIST pause

Instruction SRAM BIST pause

16

Instruction SRAM BIST start strobe

Instruction SRAM BIST running flag

15:5

Data SRAM BIST size

Data SRAM BIST size

4

Reserved (should be zero)

Data SRAM BIST complete flag

3

Reserved (should be zero)

Data SRAM BIST fail flag

2

Data SRAM BIST enable

Data SRAM BIST enable

1

Data SRAM BIST pause

Data SRAM BIST pause

0

Data SRAM BIST start strobe

Data SRAM BIST running flag

At reset, all bits are cleared LOW. BIST must be enabled before a BIST operation is started. When BIST is enabled to test one or both tightly-coupled SRAMs, the SRAM being tested is automatically disabled by clearing its enable bit in CP15 Register 1. This is to prevent the programmer inadvertently using the SRAM following a BIST operation, as the BIST algorithm corrupts the SRAM contents.

The BIST size field determines the size of the BIST operation. The value written to this field N, is decoded as follows:

BIST size in bytes = 2N+2

Some examples are shown in Table 2.6:

Table 2.6. BIST size encoding examples

Instruction RAM BIST size [31:21]

N

Size of test

000000 00001 (minimum)

1

8 bytes

000000 00100

4

64 bytes

000000 00111

7

512 bytes

000000 01000

8

1 KB

000000 01010

10

4 KB

000000 01111

15

128 KB

000000 11000 (maximum)

24

64 MB

Note

BIST size bits [31:26] should be zero.

Writing to the BIST control register with Bit[0] set initiates a data SRAM BIST operation.

Writing to the BIST control register with Bit[16] set initiates an instruction SRAM BIST operation.

Instruction and data BIST operations can be run individually or concurrently. The Size, Pause and Enable bits within the BIST control register should be set up prior to initiating a BIST operation.

Reading the BIST control register returns the status of the BIST operations. See BIST of tightly-coupled SRAM for a detailed description of the BIST support and the additional register 15 BIST registers.

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