5.4. AHB clocking

The ARM966E-S design uses a single rising edge clock CLK to time all internal activity. In many systems in which the ARM966E-S is embedded, it may be desirable to run the AHB at a lower rate. To support this requirement, the ARM966E-S requires a clock enable, HCLKEN, to time AHB transfers.

The HCLKEN input is driven high around the rising edge of the ARM966E-S CLK to indicate that this rising edge is also a rising edge of HCLK. This requires that HCLK is synchronous to the ARM966E-S CLK.

When the ARM9E-S is running from tightly-coupled SRAM or performing writes using the write buffer, the ARM966E-S HCLKEN and HREADY inputs are ignored in terms of generating the SYSCLKEN core stall signal. The core is only stalled by SRAM stall cycles or if the write buffer overflows. This means that the ARM9E-S is executing instructions at the faster CLK rate and is effectively decoupled from the HCLK domain AHB system.

If however, an AHB read access or unbuffered write is required, the core is stalled until the AHB transfer has completed. As the AHB system is being clocked by the lower rate HCLK, it is necessary to examine HCLKEN to detect when to drive out the AHB address and control to start an AHB transfer. HCLKEN is then required to detect the following rising edges of HCLK so that the BIU knows the access has completed. Figure 5.14 shows an example of an AHB read access where there is a 3:1 ratio of CLK to HCLK.

Figure 5.14. AHB 3:1 clocking example

If the slave being accessed at the HCLK rate has a multi-cycle response, the HREADY input to the ARM966E-S is driven LOW until the data is ready to be returned. The BIU must therefore perform a logical AND on the HREADY response with HCLKEN to detect that the AHB transfer has completed. When this is the case, the ARM9E-S core can then be enabled by reasserting SYSCLKEN.


When an AHB access is required, the core must be stalled until the next HCLKEN pulse is received, before it can start the access, and then until the access has completed. This stall before the start of the access is a synchronization penalty and the worst case can be expressed in CLK cycles as the CLK to CLK ratio minus 1.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0164A