6.3. MCR/MRC

These cycles look very similar to STC/LDC. An example, with a busy-wait state, is shown in Figure 6.2. First nCPMREQ is driven LOW to denote that the instruction on CPINSTR[31:0] is entering the decode stage of the pipeline. This causes the coprocessor to decode the new instruction and drive CHSDE[1:0] as required. In the next cycle nCPMREQ is driven LOW to denote that the instruction has now been issued to the execute stage. If the condition codes passes, and hence the instruction is to be executed, then the CPPASS signal is driven HIGH and the CHSDE[1:0] handshake bus is examined (it is ignored in all other cases).

Figure 6.2. MCR/MRC transfer timing with busy-wait

For any successive execute cycles the CHSEX[1:0] handshake bus is examined. When the LAST condition is observed, the instruction is committed. In the case of a MCR, the CPDOUT[31:0] bus is driven with the registered data. In the case of a MRC, CPDIN[31:0] is sampled at the end of the ARM9E-S core memory stage and written to the destination register during the next cycle.

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