6.4. Interlocked MCR

If the data for a MCR operation is not available inside the ARM9E-S core pipeline during its first decode cycle, then the ARM9E-S core pipeline will interlock for one or more cycles until the data is available. An example of this is where the register being transferred is the destination from a preceding LDR instruction.

In this situation the MCR instruction will enter the decode stage of the coprocessor pipeline, and then remain there for a number of cycles before entering the execute stage. Figure 6.3 gives an example of an interlocked MCR that also has a busy-wait state.

Figure 6.3. Interlocked MCR/MRC timing with busy-wait

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