4.2. SRAM stall cycles

Stall cycles can occur in both the instruction and data SRAMs, with one stall mechanism being shared between the SRAMs and an additional stall mechanism attributed to the I-SRAM only. Any stall requirement is detected by the SRAM control and factored into its response to the ARM966E-S system controller. The ARM9E-S SYSCLKEN input is then de-asserted until the SRAM has performed the access.

Table 4.1 shows the number of stall cycles added for different stall mechanisms.

Table 4.1. SRAM stall cycles

Number of

added cycles

Stall mechanism

1

Read follows write

1

Simultaneous instruction fetch, data read.

1

Simultaneous instruction fetch, data write.

1

I-SRAM data write followed by instruction fetch.

2

I-SRAM write followed by instruction fetch, data write.

2

I-SRAM write followed by instruction fetch, data read.

For a detailed description of SRAM stall cycles, see Appendix C SRAM Stall Cycles.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0164A
Non-Confidential