10.5. Interrupt latency calculation

The ARM9E-S has a worst-case interrupt latency figure that is listed in the ARM9E-S TRM - Programmer’s Model chapter. The number quoted assumes that the CLKEN input to the core is high, ensuring no stall cycles.

In the ARM966E-S, the best-case figure could match the latency quoted for the ARM9E-S core, if the necessary data and instructions were already in the D-SRAM and I-SRAM respectively. However, when calculating the worst-case figure, it must be assumed that the necessary data and instructions are not in the tightly-coupled SRAM and must therefore be accessed over the AHB.

In addition, the worst-case is where the write buffer is full when the interrupt occurs, requiring that the buffer drain is added to the interrupt latency calculation. The worst-case sequence for the write buffer is that five nonsequential words are to be written.

The ARM9E-S Technical Reference Manual specifies that the worst-case interrupt latency occurs when the longest LDM incurs a data abort. However, for the ARM966E-S, this is modified to be the longest LDM without a data abort. The LDM that incurs a data abort takes extra CLK cycles in the core, but the abort vector would usually be in the tightly-coupled SRAM and could be returned without introducing the extra stall cycles of an AHB access.

The longest LDM without the data abort is one which loads all the registers including the pc, which can cause a branch to a destination anywhere in memory. The branch destination must therefore be assumed to be outside of the tightly-coupled SRAM. The loads to the pc address and (pc + 1) cause additional AHB accesses which therefore produce the worst-case interrupt latency.

The pipelining of the ARM9E-S is such that two data transfers, two instruction fetches and the LDM (r0-pc) can occur before the interrupt vector is fetched. The write buffer drain must be added to this, as well as assuming that the LDM (r0-pc) crosses a 1KB boundary. Using the symbols defined in Table 10.3, the worst-case interrupt latency can be summarized in Table 10.6.

Table 10.6. Interrupt latency cycle summary

AHB access



Write buffer drain

Sync + 5(N + I)

FIQ asserted, first data transfer requested, write buffer drain stalls Core. Back to back NONSEQ writes

Simultaneous LDR/STR and instruction fetch

2 N + B

First data transfer and instruction fetch. Synchronization retained

Simultaneous LDR/STR and instruction fetch

2 N + B

Second data transfer and instruction fetch. Synchronization retained

LDM (r0-pc) crosses 1KB boundary

2 N + 14 S + 4 I

No instruction fetch at end due to Core pipeline bubble to calculate pc

Instruction fetch of (pc)

Sync + N + B

Synchronization lost due to Core internal cycle, no AHB request

Sequential instruction fetch of (pc + 1)

S + B

Synchronization retained

The calculation assumes that once the interrupt has entered the decode stage of the ARM9E-S pipeline following the instruction fetch to (pc + 1), the subsequent fetches to the interrupt vector will be serviced by the tightly-coupled SRAM, requiring a further 3 CLK cycles for the FIQ handler to enter execute. (This will not be the case if the interrupt vector resides at the HIVECS location of 0xFFFF 0000, which will require AHB access.)

The cycles from Table 10.6 are added to the 3 CLK cycles from the tightly-coupled SRAM to produce the interrupt latency equation:

Interrupt latency CLK = 2 Sync + 12 N + 15 S + 4B + 9I + 3

Rewriting in terms of R, NONSEQ, SEQ, IDLE and BUSY the equation simplifies to:

Interrupt latency CLK = R (12 NONSEQ + 15 SEQ + 15) + 1

(Where IDLE = BUSY = R as these are single HCLK cycles by definition.)

The number of CLK cycles latency can now be derived for different AHB clocking ratios and for the differing AHB slave responses that may exist in the AHB system to which the ARM966E-S interfaces. Table 10.7 gives examples of interrupt latency for systems with different CLK to HCLK ratios. For each system, slaves may have different response times to NONSEQ and SEQ transfers. The table gives some examples of different slave responses and the resultant interrupt latency in CLK cycles.

Table 10.7. Interrupt latency calculated examples


Ratio - R

Latency when


SEQ = 1

Latency when


SEQ = 1

Latency when


SEQ = 2

















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