A.5. Debug signals

Table A.4 describes the ARM966E-S debug signals.

Table A.4. Debug signals

Name

Direction

Description

DBGIR[3:0]

TAP controller instruction register

Output

These four bits reflect the current instruction loaded into the TAP controller control register. These bits change when the TAP controller is in the UPDATE-IR state.

DBGnTRST

Not test reset

Input

Internally synchronized active LOW reset signal for the Embedded ICE internal state.

DBGnTDOEN

Not DBGTDO enable

Output

When LOW, this signal denotes that the serial data is being driven out of the DBGTDO output. Normally used as an output enable for a DBGTDO pin in a packaged part.

DBGSCREG[4:0]

Output

These five bits reflect the ID number of the scan chain currently selected by the TAP controller. These bits change when the TAP controller is in the UPDATE-IR state.

DBGSDIN

External scan chain serial input data

Output

Contains the serial data to be applied to an external scan chain.

DBGSDOUT

External scan chain serial data output

Input

Contains the serial data out of an external scan chain. When an external scan chain is not connected, this signal must be tied LOW.

DBGTAPSM[3:0]

TAP controller state machine

Output

This bus reflects the current state of the TAP controller state machine.

DBGTDI

Input

Test data input for debug logic

DBGTDO

Output

Test data output from debug logic

DBGTMS

Input

Test mode select for TAP controller

COMMRX

Communications channel receive

Output

When HIGH denotes that the comms channel receive buffer contains valid data waiting to be read.

COMMTX

Communications channel transmit

Output

When HIGH, denotes that the comms channel transmit buffer is empty.

DBGACK

Debug acknowledge

Output

When HIGH indicates that the processor is in debug state.

DBGEN

Debug enable

Input

Enables the debug features of the processor. This signal should be tied LOW if debug is not required.

DBGRQI

Internal debug request

Output

Represents the debug request signal that is presented to the core debug logic. This is a combination of EDBGRQ and bit 1 of the debug control register.

EDBGRQ

External debug request

Input

An external debugger may force the processor into debug state by asserting this signal.

DBGEXT[1:0]

EmbeddedICE external input

Input

Input to the EmbeddedICE-RT logic allows breakpoints/watchpoints to be dependent on external conditions.

DBGINSTREXEC

Instruction executed

Output

Indicates that the instruction in the execute stage of the processor’s pipeline has been executed.

DBGRNG[1:0]

EmbeddedICE Rangeout

Output

Indicates that the corresponding EmbeddedICE-RT watchpoint register has matched the conditions currently present on the address, data and control buses. This signal is independent of the state of the watchpoint enable control bit.

TAPID[31:0]

Boundary scan ID code

Input

Specifies the ID code value shifted out on DBGTDO when the IDCODE instruction is entered into the TAP controller.

DBGIEBKPT

Instruction breakpoint

Input

Asserted by external hardware to halt execution of the processor for debug purposes. If HIGH at the end of an instruction fetch, it will cause the ARM966E-S to enter debug state if that instruction reaches the execute stage of the processor pipeline.

DBGDEWPT

Data watchpoint

Input

Asserted by external hardware to halt execution of the processor for debug purposes. If HIGH at the end of a data memory request cycle, it will cause the ARM966E-S to enter debug state.

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