10.4. AHB memory access cycles

When a read or non-bufferable write access to the AHB is performed, stall cycles are introduced. The number of CLK stall cycles incurred will depend on the clocking ratio of the AHB interface, the type of access being performed, and if there are further accesses to be performed. Before an AHB transfer can be initiated, the ARM966E-S must be the granted bus master. The cycle calculations in this section assume that the ARM966E-S is granted and that it is the default bus master.

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