10.2. When stall cycles do not occur

Before listing the various stall cycle scenarios, it is useful to consider the circumstances where the ARM9E-S core can run within the ARM966E-S with no stall cycles introduced by the system controller. When this is the case, the ARM966E-S is running at peak efficiency and the instruction cycles will exactly match those quoted in the ARM9E-S TRM.

The fundamental requirement for no stall cycles is that the I-SRAM is enabled and the necessary instructions have been previously programmed into it. Additionally, if the D-SRAM is enabled, it may be accessed for reads without incurring a stall penalty, even if the I-SRAM is being simultaneously accessed for an instruction fetch.

When a write is performed, the access may also be zero stall if the write buffer is used and there is space available. If the write is to the D-SRAM, the write will also be single cycle in most circumstances, and any store multiple to the D-SRAM can be executed as one write per cycle. As long as these writes are not to the I-SRAM address space, instruction fetches from the I-SRAM can be performed simultaneously without incurring a stall penalty.

To maximize performance, it is therefore desirable to ensure that frequently accessed code is pre-loaded into the I-SRAM and that data accesses map to the D-SRAM address space. It is also advisable to enable the write buffer and use bufferable areas of memory where possible, when AHB writes are performed.


If the data interface of the ARM9E-S core accesses the I-SRAM memory, in most cases stall cycles will result. An example of where this type of access is unavoidable, is the fetching of in line code literals from the I-SRAM.

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