10.1. Introduction to instruction cycle timings

The ARM9E-S core within the ARM966E-S implements a pipelined architecture where several instructions in different pipeline stages overlap. The tables in the ARM9E-S Technical Reference Manual (Chapter 6 - Instruction cycle timings) show the number of cycles required by an instruction, once it has reached the execute stage of the ARM9E-S core pipeline.

The instruction cycle timing numbers quoted in the ARM9E-S TRM assume that the ARM9E-S is permanently enabled with the CLKEN input tied high. This implies that both instruction and data memory connected to the ARM9E-S are able to perform zero wait state responses to all accesses.

In a system such as the ARM966E-S, the CLKEN input to the ARM9E-S core may be pulled low to stall the processor until the memory system is able to respond to the access. These stall cycles must be taken into account when calculating the ARM966E-S instruction cycle timings.

Stall cycles are introduced by the ARM966E-S system controller in the following circumstances:

This chapter lists the cycle counts for the both normal operation and the above scenarios.

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