10.3. Tightly-coupled SRAM cycles

The circumstances in which the internal tightly-coupled SRAM can stall are covered in depth in SRAM stall cycles. This section lists the stall cycle counts for accesses to one or both of the SRAMs.

Table 10.1 shows the stall cycles incurred when accessing the I-SRAM. In most cases the data accesses will be to the D-SRAM so the stall penalties listed will not be incurred.

Table 10.1. I-SRAM access

Instruction sequence

Stalls

Comment

Single instruction fetch

0

Assuming no data interface access to I-SRAM

Sequential instruction fetch

0

Assuming no data interface access to I-SRAM

LDR, no instruction fetch

0

Assuming no previous I-SRAM store

LDR, simultaneous instruction fetch

1

Simultaneous instruction fetch request causes stall

LDM, instruction fetch in parallel with final load

1

Simultaneous instruction fetch request at end of LDM causes stall

STR, no instruction fetch

0

Assuming no previous ISRAM store

STR simultaneous instruction fetch

2

Two cycle write performed prior to instruction fetch

STR followed by instruction fetch

1

Stall occurs due to second cycle of store

STR followed by simultaneous, instruction fetch LDR

2

Stall due to second cycle of store plus simultaneous load and instruction fetch request

STR followed by simultaneous instruction fetch, STR

2

Stall due to second cycle of second store plus instruction fetch request

STR followed by LDR/STR, no instruction fetch

1

Stall due to second cycle of store

STM, instruction fetch in parallel with final store

2

Simultaneous instruction fetch request must wait for second cycle of final write to complete

The D-SRAM can only be accessed by the ARM9E-S data interface so there are no simultaneous access contentions as found in the I-SRAM. Table 10.2 shows the stall cycles that can occur when accessing the D-SRAM.

Table 10.2. D-SRAM access

Data access

Stalls

Comment

LDR

0

D-SRAM provides single cycle response

LDM

0

D-SRAM provides single cycle response to each word

LDR/LDM followed by any load or store

0

D-SRAM provides single cycle response

STR

0

Assuming no following load

STM

0

Assuming no following load

STR/STM followed by STR/STM

0

Pipelined addresses allow back to back stores/store multiples

STR/STM followed by LDR/LDM

1

Second cycle of write causes stall before load can be performed

Note

All internal SRAM stall cycles are in terms of the CLK and are therefore not affected by the speed of the external AHB interface.

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