C.1.2. Additional Instruction SRAM stalls

The I-SRAM can stall in addition to the D-SRAM stalls in the following ways:

Simultaneous instruction fetch, data read

The ARM9E-S data interface is able to access the I-SRAM for programming purposes and for access to literal tables during program execution.

It is possible for the ARM9E-S to issue a simultaneous instruction and data request, and if the data request addresses the I-SRAM, a stall cycle will be required. See Figure C.3.

Figure C.3. Simultaneous instruction fetch, data read

Note

In the case of simultaneous instruction and data SRAM access requests from the ARM9E-S core, the data request is always performed first, followed by the instruction request. The core is disabled until both accesses have completed.

Simultaneous instruction fetch, data write

If the ARM9E-S performs a simultaneous data write and instruction fetch that both map to I-SRAM address space, two stall cycles occur. The first cycle is to allow for the pipelined write, the second cycle allows for the instruction fetch. The core cannot be enabled until both accesses have completed. See Figure C.4.

Figure C.4. Simultaneous instruction fetch, data write

I-SRAM data write followed by instruction fetch

This class of stall occurs when a data write to the I-SRAM address space is performed, followed by an instruction fetch request in the next cycle. It is similar to the generic read follows write scenario of each SRAM except that the read is an instruction fetch rather than a data load. The instruction fetch must be held off until the write has completed, requiring that the ARM9E-S core is stalled for a cycle. See Figure C.5.

Figure C.5. I-SRAM data write followed by instruction fetch

I-SRAM write followed by instruction fetch, data write

This case is where a write is taking place to the I-SRAM that is immediately followed by both an instruction fetch and a data write. The second write gets performed immediately after the current write without penalty. However, the core must be stalled until both the second write and instruction fetch have completed, so there are two stall cycles. See Figure C.6.

Figure C.6. I-SRAM write followed by instruction fetch, data write

I-SRAM write followed by instruction fetch, data write

The final stall scenario is where a write is taking place to the I-SRAM that is immediately followed by both an instruction fetch and a data read. This has the same two stall cycle response as the previous scenario, although the I-SRAM control behaves differently. The first write must complete before the data read can be performed. The instruction fetch can then be performed in the next cycle. See Figure C.7.

Figure C.7. I-SRAM write followed by instruction fetch, data read

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