4.4.1. Example SRAM interfaces

The example wrapper supplied by ARM contains three ram interface examples. All of the interface modifications are done in the IRamIF.v and the DRamIF.v blocks for the I-SRAM and D-SRAM respectively.

All of these examples assume a 32KByte SRAM (8K words x 4bytes). The example is shown for the I-SRAM, the D-SRAM interface is identical.

Example 4.1. ONESEGX32

This example is for the simplest interface case. To use this case, the SRAM must consist of a single word wide RAM that has byte-write control.

Only single ChipSelect and WriteEnable signals are required. See Figure 4.3.

Figure 4.3. ONESEGX32 Interface

Example 4.2. FOURSEGX32

This example is for the case where it is not possible to construct the SRAM from a single physical block due to either layout constraints, generator constraints or because a single SRAM segment does not meet timing constraints.

Separate chip select signals are required for each SRAM block, see Figure 4.4.

Figure 4.4. FOURSEGX32 Interface

Note

The generation of separate chip select signals for each SRAM block ensures good power performance, because only the segment being accessed is enabled.

The SRAM address is 11 bits in this example (compared with the 13 bit address in Example1). RamAddr[12:11] are used to generate separate chip selects for each segment.

If it is not possible to have separate chip select signals for each block of RAM, for example if the RAM is asynchronous, then separate write enable signals will be required for each segment. The use of asynchronous rams is not recommended due to the increased power consumption of this solution.

Note

The wrapper RTL does not support asynchronous RAMs.

Example 4.3. FOURSEGX8

This example is for the case where a SRAM does not support byte-writes and the SRAM needs to be split into four byte wide segments. In order to give an example of the most complex interface possible, the FOURSEGX8 example assumes that each byte-wide SRAM needs to be split into four blocks (as for the word-wide SRAM in Example 4.2).

As for Example 4.2, the SRAM Address is 11 bits. Bits [12:11] of the address are used to decode which of the four word wide RAMs is selected. ByteWrite[3:0] is used (inside IRamIF.v) to decode each word wide chip select into four separate chip select signals, one for each byte of the word. See Figure 4.5.

Figure 4.5. FOURSEGX8 Interface

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