5.3.2. ARM966E-S transfer descriptions

The ARM966E-S BIU performs a subset of the possible AHB bus transfers available. The transfers that can be performed and some back to back transfer cases are considered in this section.

All timing examples assume one-to-one clocking where the ARM966E-S and AHB share the same clock. See AHB clocking for details of AHB clocking modes.

Burst transfers

As the ARM966E-S does not implement cache memory, burst transfers of fixed length which are commonly used for cache linefill and data cache writeback are not supported. All burst accesses are defined to be INCRemental (HBURST[2:0] = 001), as the only indication that the ARM966E-S has about the sequentiality of the access is the DMORE output from the ARM9E-S core. This output indicates that there is at least one more access following the current access, but does not indicate how many further sequential accesses can be expected.

Bus request

At the start of every AHB access, the ARM966E-S requests access to the bus by asserting HBUSREQ to the arbiter. It must then wait for an acknowledge signal from the arbiter (HGRANT), before beginning the transfer on the next rising edge of HCLK.

Figure 5.2. Sequential instruction fetches, after being granted the bus

In Figure 5.2, the slave being addressed has a single cycle response to the read access and therefore drives the HREADY response high back to the ARM966E-S BIU.

Sequential instruction fetch

When the ARM9E-S fetches instructions from the AHB address space or if the tightly-coupled I-SRAM is disabled, AHB read transfers are initiated by the BIU. The instruction interface does not have the benefit of a pipelined MORE signal, so the BIU cannot detect a sequential access and use an address incrementer to perform back to back sequential cycles. Instead, a BUSY cycle is used after each transfer to allow the core instruction address to go through the BIU pipeline onto the AHB and to examine the ARM9E-S ISEQ output to detect whether the address is sequential.

Figure 5.3. Sequential instruction fetches, no AHB data access required

Figure 5.3 shows a series of sequential instruction fetches where any data access being performed by the ARM9E-S is using the tightly-coupled SRAM and are therefore not interfering with the instruction fetches.

Nonsequential instruction fetch

When a sequence of instruction fetches goes nonsequential (that is, when a branch is in execute), the BIU must break up the SEQ/BUSY transfer cycles to perform a NONSEQ type transfer. The sequence for this is shown in Figure 5.4.

Figure 5.4. Nonsequential instruction fetch, no external data access

Again, Figure 5.4 assumes that any ARM9E-S data interface activity is accessing the tightly-coupled SRAM.

Back to back LDR or STR accesses

Figure 5.5 shows ARM966E-S bus activity when a sequence of LDR instructions is executed.

Figure 5.5. Back to back LDR, no external instruction access

A series of NONSEQ/IDLE transfers is indicated for each access.

Even though the transfers may be to sequential addresses, each access is treated as a separate nonsequential transfer. Figure 5.5 assumes that all instruction fetches from the ARM9E-S core are being serviced by the I-SRAM.

Note

An identical series of NONSEQ/IDLE transfers would be seen if executing a sequence of back to back STR instructions.

Simultaneous instruction and data request

When the ARM9E-S makes a simultaneous instruction and data request, both of which lie in AHB memory space, the BIU must arbitrate between the two accesses. The data access is always completed first, stalling the ARM9E-S until the instruction fetch completes.

Figure 5.6 shows an example of an STR instruction causing a simultaneous instruction and data request.

Figure 5.6. Simultaneous instruction and data requests

During the cycle that [IA-3] is first driven onto HADDR, the BIU detects a simultaneous data request. [IA-3] fetch is suspended until the data access has completed.

Note

In this situation, the BIU goes direct from BUSY to NONSEQ on HTRANS.

STM timing

Figure 5.7 shows the timing for an STM instruction, transferring 3 words. Outputs to the AHB are not driven during IDLE cycles, and so hold their previous value. This includes the HBURST output, which continues to indicate INCRemental until the next nonsequential transfer. This should not cause any confusion to other AHB components as HTRANS indicates IDLE cycles.

Figure 5.7. Single STM, no instruction fetch

Note

HBUSREQ is driven low after one IDLE cycle which is always inserted after an STM which is not immediately followed by an external instruction access. An STM, immediately followed by any other AHB data access, also results in one IDLE cycle being inserted between the two accesses.

LDM timing

Figure 5.8 shows the timing for an LDM instruction, transferring 3 words.

Figure 5.8. Single LDM, no instruction access

Note

HBUSREQ is driven low after two IDLE cycles which are always inserted after a LDM which is not immediately followed by an external instruction access. An LDM, immediately followed by any other AHB data access, also results in two IDLE cycles being inserted between the two accesses.

STM followed by instruction fetch

Figure 5.9 shows an example of an STM transferring three words, immediately followed by an instruction fetch. The instruction read begins with a NONSEQ-BUSY sequence after the final sequential data access. In this example, subsequent instruction fetches are sequential.

Figure 5.9. Single STM, followed by sequential instruction fetch

Note

The single IDLE cycle that normally occurs at the end of an STM has been filled by the NONSEQ cycle for the instruction fetch.

LDM followed by instruction fetch

Figure 5.10 shows an example of a LDM transferring three words, immediately followed by an instruction fetch. A single IDLE cycle is inserted after the final sequential data access, and instruction fetch begins with a NONSEQ-BUSY sequence.

Figure 5.10. Single LDM followed by sequential instruction fetch.

Note

The NONSEQ cycle of the instruction fetch replaces the second IDLE cycle that occurs when an AHB data access is required following the LDM.

STM crossing a 1KB boundary

AMBA Rev.2 specifies that sequential accesses should not cross 1KB boundaries. The ARM966E-S splits sequential accesses which cross a 1KB boundary into two sets of apparently separate accesses.

Figure 5.11 shows bus activity when a STM writing four words, crosses a 1KB boundary. DA-3 is the first address in a new 1KB region. The two sets of transfers each begin with a nonsequential access type, and are separated by an IDLE cycle.

Figure 5.11. Single STM, crossing a 1KB boundary.

LDM crossing a 1KB boundary

Figure 5.12 shows bus activity when a LDM reading four words, crosses a 1KB boundary. The two sets of transfers each begin with a nonsequential access type, and are separated by two IDLE cycles.

Figure 5.12. Single LDM, crossing a 1KB boundary

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