5.4.1. CLK to HCLK skew

It can be seen that the ARM966E-S drives out the AHB address on the rising edge of CLK when the HCLKEN input is true. The AHB outputs will therefore have output hold and delay values relative to CLK. However, these outputs are used in the AHB system where HCLK is used to time the transfers. Similarly, inputs to the ARM966E-S are timed relative to HCLK but are sampled within the ARM966E-S with CLK. This leads to hold time issues from CLK to HCLK on outputs and from HCLK to CLK on inputs. In order to minimize this effect the skew between HCLK and CLK should be minimized.

Clock tree insertion at top level

Considering the skew issue in more detail, the ARM966E-S will have a clock tree inserted to allow an evenly distributed clock to be driven to all the registers in the design. The registers that drive out AHB outputs and sample AHB inputs will therefore be timed off CLK’ at the bottom of the inserted clock tree and subject to the clock tree insertion delay. To maximize performance, when the ARM966E-S is embedded in an AHB system, the clock generation logic to produce HCLK should be constrained such that it matches the insertion delay of the clock tree within the ARM966E-S. This can easily be achieved by a clock tree insertion tool if the clock tree is inserted for the ARM966E-S and the embedded system at the same time (top level insertion).

Figure 5.15 shows an example of an AHB slave connected to the ARM966E-S.

Figure 5.15. ARM966E-S CLK - AHB HCLK sampling

In this example, the slave peripheral will have an input setup and hold and an output hold and valid time relative to HCLK. The ARM966E-S will have an input setup and hold and an output hold and valid relative to CLK’, the clock at the bottom of the clock tree. Clock tree insertion should be used to position the HCLK to match CLK’ for optimal performance.

Hierarchical clock tree insertion

If the ARM966E-S has clock tree insertion performed before embedding it, buffers will have been added on input data to match the clock tree so that the setup and hold is relative to the top level CLK. This is guaranteed to be safe at the expense of extra buffers in the data input path.

The HCLK domain AHB peripherals must still meet the ARM966E-S input setup and hold requirements. As the ARM966E-S inputs and outputs are now relative to CLK, the outputs will appear comparatively later by the value of the insertion delay. This ultimately leads to lower AHB performance.

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