7.1.2. Clocks

The system and test clocks must be synchronized externally to the ARM966E-S macrocell. The ARM Multi-ICE debug agent directly supports one or more cores within an ASIC design. To synchronize off-chip debug clocking with the ARM966E‑S macrocell requires a three‑stage synchronizer. The off-chip device (for example, Multi-ICE) issues a TCK signal, and waits for the RTCK (Returned TCK) signal to come back. Synchronization is maintained because the off-chip device does not progress to the next TCK until after RTCK is received.

Figure 7.1 shows this synchronization:

Figure 7.1. Clock synchronization

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