7.4.3. Watchpoints

Entry into debug state following a watchpointed memory access is imprecise. This is necessary because of the nature of the pipeline.

External logic, such as external watchpoint comparators, may be built to extend the functionality of the EmbeddedICE-RT logic. Their output must be applied to the DBGDEWPT input. This signal is simply ORed with the internally-generated Watchpoint signal before being applied to the ARM9E‑S core control logic The timing of the input makes it unlikely that data-dependent external watchpoints will be possible.

After a watchpointed access, the next instruction in the processor pipeline is always allowed to complete execution. Where this instruction is a single‑cycle data‑processing instruction, entry into debug state is delayed for one cycle while the instruction completes. The timing of debug entry following a watchpointed load in this case is shown in Figure 7.5.

Figure 7.5. Watchpoint entry with data processing instruction


Although instruction 5 enters the execute stage, it is not executed, and there is no state update as a result of this instruction. Once the debugging session is complete, normal continuation would involve a return to instruction 5, the next instruction in the code sequence which has not yet been executed.

The instruction following the instruction which generated the watchpoint could have modified the Program Counter (PC). If this has happened, it will not be possible to determine the instruction which caused the watchpoint. A timing diagram showing debug entry after a watchpoint where the next instruction is a branch is shown in Figure 7.6. However, it is always possible to restart the processor.

Once the processor has entered debug state, the ARM9E‑S core may be interrogated to determine its state. In the case of a watchpoint, the PC contains a value that is five instructions on from the address of the next instruction to be executed. Therefore, if on entry to debug state, in ARM state, the instruction SUB PC, PC, #20 is scanned in and the processor restarted, execution flow would return to the next instruction in the code sequence.

Figure 7.6. Watchpoint entry with branch

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