7.9.2. Debug comms channel status register

The debug comms channel status register is read only. It controls synchronized handshaking between the processor and the debugger. The debug comms channel status register is shown in Figure 7.8.

Figure 7.8. Debug comms channel status register

The function of each register bit is described below:

Bits 31:28

Contain a fixed pattern that denotes the EmbeddedICE-RT version number (in this case 0011).

Bits 27:2

Are reserved.

Bit 1

Denotes whether the comms data write register is available (from the viewpoint of the processor). If, from the point of view of the processor, the comms data write register is free (W=0), new data may be written. If the register is not free (W=1), the processor must poll until W=0. From the point of view of the debugger, when W=1, some new data has been written that may then be scanned out.

Bit 0

Denotes whether there is new data in the comms data read register. If, from the point of view of the processor, R=1, there is some new data which may be read using an MRC instruction. From the point of view of the debugger, if R=0, the comms data read register is free, and new data may be placed there through the scan chain. If R=1, this denotes that data previously placed there through the scan chain has not been collected by the processor, and so the debugger must wait.

From the point of view of the debugger, the registers are accessed using the scan chain in the usual way. From the point of view of the processor, these registers are accessed using coprocessor register transfer instructions.

You should use the following instructions:

MRC p14, 0, Rd, c0, c0

This returns the debug comms control register into Rd.

MCR p14, 0, Rn, c1, c0

This writes the value in Rn to the comms data write register.

MRC p14, 0, Rd, c1, c0

This returns the debug data read register into Rd.

Because the Thumb instruction set does not contain coprocessor instructions, you are advised to access this data using SWI instructions when in Thumb state.

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