9.3.1. BIST control register

The CP15 register 15 BIST control register controls the operation of the SRAM memory BIST. Before initiating a BIST test, a MCR is first performed to the BIST control register to set up the size of the test and enable the SRAM to be tested. A further MCR is required to initiate the test.

The current status of a BIST test and result of a completed test can be accessed by performing an MRC to the BIST control register. This returns flags to indicate that a test is:

As well as returning the state for the size of the test and SRAM enable status, having completed a BIST test, if the programmer wishes to use the SRAM for functional operation the BIST enable must first be cleared by writing to the BIST control register. The SRAM must then be re-enabled by writing to CP15 register 1. This is necessary as the BIST test enable automatically clears the functional enable.


Clearing the functional SRAM enable when BIST is enabled prevents the programmer from trying to run from tightly coupled SRAM following a BIST test, without having first reprogrammed the SRAM. This is necessary as the BIST algorithm corrupts all tested SRAM locations.

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