10.4.1. Synchronization penalty

At the start of an AHB access, the Bus Interface Unit (BIU) within the ARM966E-S must wait for the first rising edge of HCLK (the HCLKEN input is true) before it can broadcast the necessary AHB control and address information for the access. This delay is the synchronization penalty. The best case is that in the cycle in which the AHB access is requested, the HCLKEN input is high, incurring a zero cycle synchronization penalty. The worst case is where the HCLKEN is high in the cycle just before the AHB access is required. The ARM966E-S must then wait until the next assertion of HCLKEN which will be R - 1 cycles later, where R is the CLK to HCLK ratio.

If the AHB must be accessed for two transfers which were requested simultaneously by the ARM9E-S core (that is, a simultaneous instruction fetch and data load), the BIU stays synchronized after the first transfer so that the penalty is only incurred for the first access. If the transfer is part of a burst (STM/LDM) or a sequential instruction fetch sequence, again the BIU stays synchronized between each transfer to minimize synchronization penalty.


If the clock ratio R = 1, the HCLKEN input to the ARM966E-S is tied high so there is no synchronization penalty incurred when accessing the AHB.

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