10.4.2. AHB transfer types

The ARM966E-S is able to perform IDLE, BUSY, NONSEQ and SEQ transfers. Depending on the implementation of the AHB system to which the ARM966E-S is connected, a varying number of HCLK cycles will be required for the NONSEQand SEQ transfers. Typically, a NONSEQ cycle will require a two cycle response from the selected slave, whereas a SEQ cycle can be handled in a single cycle. Both the IDLE and BUSY cycles take one HCLK cycle by definition.

For each HCLK cycle required by the AHB transfer, R internal CLK cycles are taken. The AHB transfer cycles are therefore converted to CLK by multiplying by R, the CLK to HCLK ratio, as shown in Table 10.3.

Table 10.3. Key to tables

Symbol

Meaning in terms of CLK cycles

Sync

Worst-case synchronization penalty (= R - 1)

S

HCLK cycles required for a SEQ transfer x R

N

HCLK cycles required for a NONSEQ transfer x R

I

HCLK cycle required for an IDLE cycle (= R)

B

HCLK cycle required for a BUSY cycle (= R)

n

Number of words accessed by the transfer

Table 10.4 lists the types of AHB transfers performed by the ARM966E-S and the number of CLK cycles required to perform them. This table indicates cycles where the ARM9E-S core must be stalled until one or more AHB accesses have completed, that is, for reads and unbuffered writes.

Table 10.4. AHB read and unbuffered write transfer cycles

AHB access

Cycles

Comment

Start of sequential instruction fetch of n words

Sync + N + B + (n - 1)(S + B)

Assumes no AHB load or store activity

Nonsequential instruction fetch

Sync + N + B

Assumes no AHB load or store activity

Nonsequential instruction fetch follows sequential instruction fetch

N + B

Assumes no AHB load or store activity

Single LDR or STR

Sync + N + I

Assumes no AHB instruction fetch

Back to back LDR/LDR, LDR/STR, STR/STR, STR/LDR

Sync + 2(N + I)

Assumes no AHB instruction fetch. Synchronization penalty for first transfer only

Simultaneous LDR/STR and instruction fetch

Sync + 2 N + B

Optimization replaces IDLEcycle after load/store with NONSEQ of instruction fetch

STM of n words

Sync + N + (n - 1) S + I

Assumes no AHB instruction fetch

STM of n words, simultaneous instruction fetch at end

Sync + 2 N + (n - 1) S + B

Optimization replaces IDLE cycle after final stored word with NONSEQ of instruction fetch

STM of n words crosses 1KB region

Sync + 2 N + (n - 2) S + 2 I

Assumes no AHB instruction fetch, sequentiality broken on boundary

LDM of n words

Sync + N + (n - 1) S + 2 I

Assumes no AHB instruction fetch. LDM requires extra IDLE at end of transfer to re-sample core interface

LDM of n words, simultaneous instruction fetch at end

Sync + 2 N + (n - 1) S + I + B

Optimization replaces second IDLE cycle after final loaded word with NONSEQ of instruction fetch

LDM of n words crosses 1KB region

Sync + 2 N + (n - 2) S + 4 I

Assumes no AHB instruction fetch, sequentiality broken on boundary

See AHB bus master interface for diagrams of the cycles listed above.

Table 10.5 shows the cycles required to perform buffered writes. These writes usually take place in parallel with program execution and the ARM9E-S core is not stalled while the buffered writes take place. However, whenever a load or instruction fetch to the AHB is required, the core is stalled and the write buffer drained before program execution can continue.

Table 10.5. AHB buffered writes cycles

AHB access

Cycles

Comment

Single STR

Sync + N + I

Assumes no following AHB instruction fetch

Back to back STR/STR

Sync + 2(N + I)

Assumes no following AHB instruction fetch

STM

Sync + N + (n -1) S + I

Assumes no following AHB instruction fetch

Last STR in write buffer drain followed by unbuffered data access

2 (N + I)

Core stalled until write buffer empty and data access has been performed

Last STR in write buffer drain followed by instruction fetch

2 N + B

Optimization replaces IDLE cycle after store with NONSEQ of instruction fetch

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