7.9.3. Comms channel monitor mode debug status register

The coprocessor 14 debug status register is provided for use by a debug monitor when the ARM9E-S is configured into monitor mode.

The coprocessor 14 debug status register is a 1-bit wide read/write register having the following format:

Figure 7.9. Coprocessor 14 debug status register format

Bit 0 of the register, the DbgAbt bit, indicates whether the processor took a prefetch or data abort in the past because of a breakpoint or watchpoint. If the ARM9E-S core takes a prefetch abort as a result of a breakpoint or watchpoint, then the bit will be set. If on a particular instruction or data fetch, both the debug abort and external abort signals are asserted, the external abort takes priority and the DbgAbt bit is not set. The DbgAbt bit may be read/written by the user by means of MRC/MCR instructions.

A typical use of this bit would be by a real-time debug aware abort handler. This would examine the DbgAbt bit to determine whether the abort was externally or internally generated. If the DbgAbt bit was set, the abort handler would initiate communication with the debugger over the comms channel.

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