ARM966E-S Technical Reference Manual


Table of Contents

Preface
About this document
Intended audience
Using this manual
Conventions
Further reading
ARM publications
Other publications
Feedback
Feedback on the ARM966E-S
Feedback on the ARM966E-S
1. Introduction
1.1. About the ARM966E-S
1.2. Microprocessor block diagram
2. Programmer’s Model
2.1. About the programmer’s model
2.2. About the ARM9E-S programmer’s model
2.2.1. Data Abort model
2.3. ARM966E-S CP15 registers
2.3.1. CP15 register map summary
2.3.2. Register 0: ID code
2.3.3. Register 1: Control register
2.3.4. Register 7: Core control
2.3.5. Register 15: Test
3. Memory Map
3.1. About the ARM966E-S Memory Map
3.2. Tightly-coupled SRAM address space
3.3. Bufferable write address space
4. Tightly-coupled SRAM
4.1. ARM966E-S SRAM requirements
4.2. SRAM stall cycles
4.3. Enabling the SRAM
4.3.1. Using INITRAM input pin
4.3.2. Using CP15 control register
4.4. ARM966E-S SRAM wrapper
4.4.1. Example SRAM interfaces
5. Bus Interface Unit
5.1. About the BIU and write buffer
5.2. Write buffer operation
5.2.1. Committing write data to the write buffer
5.2.2. Draining write data from the write buffer
5.2.3. Enabling the write buffer
5.2.4. Disabling the write buffer
5.3. AHB bus master interface
5.3.1. Overview of AHB
5.3.2. ARM966E-S transfer descriptions
5.3.3. SWP instruction
5.4. AHB clocking
5.4.1. CLK to HCLK skew
6. Coprocessor Interface
6.1. About the coprocessor interface
6.1.1. Synchronizing the external coprocessor pipeline
6.1.2. External coprocessor clocking
6.2. LDC/STC
6.2.1. Coprocessor handshake states
6.2.2. Coprocessor handshake encoding
6.2.3. Multiple external coprocessors
6.3. MCR/MRC
6.4. Interlocked MCR
6.5. CDP
6.6. Privileged instructions
6.7. Busy-waiting and interrupts
7. Debug Support
7.1. Overview of the debug interface
7.1.1. Stages of debug
7.1.2. Clocks
7.2. Debug systems
7.2.1. The debug host
7.2.2. The protocol converter
7.2.3. ARM966E‑S debug target
7.3. ARM966E-S scan chain 15
7.4. Debug interface signals
7.4.1. Entry into debug state on breakpoint
7.4.2. Breakpoints and exceptions
7.4.3. Watchpoints
7.4.4. Watchpoints and exceptions
7.4.5. Debug request
7.4.6. Actions of the ARM9E‑S in debug state
7.5. ARM9E‑S core clock domains
7.6. Determining the core and system state
7.7. Overview of EmbeddedICE-RT
7.8. Disabling EmbeddedICE-RT
7.9. The debug communications channel
7.9.1. Debug comms channel registers
7.9.2. Debug comms channel status register
7.9.3. Comms channel monitor mode debug status register
7.9.4. Communications via the comms channel
7.10. Monitor mode debug
7.11. Further reading - debug in depth
8. ETM Interface
8.1. About the ETM interface
8.2. Enabling the ETM interface
9. Test Support
9.1. About the ARM966E-S test methodology
9.2. Scan insertion and ATPG
9.2.1. ARM966E-S INTEST wrapper
9.3. BIST of tightly-coupled SRAM
9.3.1. BIST control register
9.3.2. BIST address and general registers
9.3.3. Pause modes
10. Instruction Cycle Timings
10.1. Introduction to instruction cycle timings
10.2. When stall cycles do not occur
10.3. Tightly-coupled SRAM cycles
10.4. AHB memory access cycles
10.4.1. Synchronization penalty
10.4.2. AHB transfer types
10.5. Interrupt latency calculation
A. Signal Descriptions
A.1. Signal properties and requirements
A.2. Clock interface signals
A.3. AHB signals
A.4. Coprocessor interface signals
A.5. Debug signals
A.6. Miscellaneous signals
A.7. ETM interface signals
A.8. INTEST wrapper signals
B. AC Parameters
B.1. Timing diagrams
B.2. AC timing parameter definitions
C. SRAM Stall Cycles
C.1. About SRAM stall cycles
C.1.1. Read-follows-write
C.1.2. Additional Instruction SRAM stalls

List of Figures

1. Key to timing diagram conventions
1.1. ARM966E-S block diagram
3.1. ARM966E-S memory map
3.2. I-SRAM aliasing example
4.1. SRAM read cycle
4.2. ARM966E-S SRAM hierarchy
4.3. ONESEGX32 Interface
4.4. FOURSEGX32 Interface
4.5. FOURSEGX8 Interface
5.1. Write buffer FIFO content example
5.2. Sequential instruction fetches, after being granted the bus
5.3. Sequential instruction fetches, no AHB data access required
5.4. Nonsequential instruction fetch, no external data access
5.5. Back to back LDR, no external instruction access
5.6. Simultaneous instruction and data requests
5.7. Single STM, no instruction fetch
5.8. Single LDM, no instruction access
5.9. Single STM, followed by sequential instruction fetch
5.10. Single LDM followed by sequential instruction fetch.
5.11. Single STM, crossing a 1KB boundary.
5.12. Single LDM, crossing a 1KB boundary
5.13. SWP instruction
5.14. AHB 3:1 clocking example
5.15. ARM966E-S CLK - AHB HCLK sampling
6.1. LDC/STC cycle timing
6.2. MCR/MRC transfer timing with busy-wait
6.3. Interlocked MCR/MRC timing with busy-wait
6.4. Late cancelled CDP
6.5. Privileged instructions
6.6. Busy-waiting and interrupts
7.1. Clock synchronization
7.2. Typical debug system
7.3. ARM9E‑S block diagram
7.4. Breakpoint timing
7.5. Watchpoint entry with data processing instruction
7.6. Watchpoint entry with branch
7.7. The ARM9E‑S, TAP controller and EmbeddedICE-RT
7.8. Debug comms channel status register
7.9. Coprocessor 14 debug status register format
8.1. ARM966E-S ETM interface
B.1. Clock, reset and AHB enable timing
B.2. AHB bus request and grant related timing
B.3. AHB bus master timing
B.4. Coprocessor interface timing
B.5. Debug interface timing
B.6. JTAG interface timing
B.7. DBGSDOUT to DBGTDO timing
B.8. Exception and configuration timing
B.9. INTEST wrapper timing
B.10. ETM interface timing
C.1. SRAM write cycle
C.2. Read follows write
C.3. Simultaneous instruction fetch, data read
C.4. Simultaneous instruction fetch, data write
C.5. I-SRAM data write followed by instruction fetch
C.6. I-SRAM write followed by instruction fetch, data write
C.7. I-SRAM write followed by instruction fetch, data read

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A13 December 1999First release
Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0164A
Non-Confidential