ARM9E-S Technical Reference Manual

(Rev 1)

Table of Contents

About this document
Intended audience
Using this manual
Typographical conventions
Timing diagram conventions
Further reading
ARM publications
Other publications
Feedback on the ARM9E-S
Feedback on the ARM9E-S Technical Reference Manual
1. Introduction
1.1. About the ARM9E-S
1.1.1. The instruction pipeline
1.1.2. Memory access
1.1.3. Forwarding, interlocking and data dependencies
1.2. ARM9E-S architecture
1.2.1. Instruction compression
1.2.2. The Thumb instruction set
1.3. ARM9E-S block, core, and interface diagrams
1.4. ARM9E-S instruction set summary
1.4.1. ARM instruction set summary
1.4.2. Thumb instruction set summary
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.2.2. Interworking ARM and Thumb state
2.3. Memory formats
2.3.1. Big-endian format
2.3.2. Little-endian format
2.4. Instruction length
2.5. Data types
2.6. Operating modes
2.7. Registers
2.7.1. The ARM state register set
2.7.2. The Thumb state register set
2.7.3. The relationship between ARM state and Thumb state registers
2.7.4. Accessing high registers in Thumb state
2.8. The program status registers
2.8.1. The condition code flags
2.8.2. The control bits
2.8.3. Reserved bits
2.9. Exceptions
2.9.1. Exception entry and exit summary
2.9.2. Entering an exception
2.9.3. Leaving an exception
2.9.4. Reset
2.9.5. Fast interrupt request
2.9.6. Interrupt request
2.9.7. Aborts
2.9.8. Software interrupt instruction
2.9.9. Undefined instruction
2.9.10. Breakpoint instruction (BKPT)
2.9.11. Exception vectors
2.9.12. Exception priorities
3. Device Reset
3.1. About device reset
3.2. Reset modes
3.2.1. Power-on reset
3.2.2. CPU reset
3.2.3. EmbeddedICE-RT reset
3.2.4. Normal operation
3.3. ARM9E-S behavior on exit from reset
4. Memory Interface
4.1. About the memory interface
4.2. Instruction interface
4.2.1. Instruction interface signals
4.3. Instruction interface addressing signals
4.3.1. IA[31:1]
4.3.2. ITBIT
4.3.3. InTRANS
4.3.4. InM[4:0]
4.4. Instruction interface data timed signals
4.4.1. INSTR[31:0]
4.4.2. IABORT
4.5. Endian effects for instruction fetches
4.6. Instruction interface cycle types
4.6.1. Instruction interface, nonsequential cycles
4.6.2. Instruction interface, sequential cycles
4.6.3. Instruction interface, internal cycles
4.6.4. Instruction interface, merged I-S cycles
4.7. Data interface
4.7.1. Data interface signals
4.8. Data interface addressing signals
4.8.1. DA[31:0]
4.8.2. DnRW
4.8.3. DMAS[1:0]
4.8.4. DnTRANS
4.8.5. DLOCK
4.8.6. DnM[4:0]
4.9. Data interface data timed signals
4.9.1. WDATA[31:0]
4.9.2. RDATA[31:0]
4.9.3. DABORT
4.9.4. Byte and halfword accesses
4.10. Data interface cycle types
4.10.1. Data interface, nonsequential cycles
4.10.2. Data interface, sequential cycles
4.10.3. Data interface, internal cycles
4.10.4. Data interface, merged I-S cycles
4.10.5. Data interface, coprocessor register transfer cycles
4.11. Endian effects for data transfers
4.11.1. Writes
4.11.2. Reads
4.12. Use of CLKEN to control bus cycles
4.12.1. Withdrawal of memory requests in waited cycles
5. Interrupts
5.1. About interrupts
5.2. Hardware interface
5.2.1. Generating an interrupt
5.2.2. Synchronization
5.2.3. Re-enabling interrupts after an interrupt exception
5.2.4. Interrupt registers
5.3. Maximum interrupt latency
5.4. Minimum interrupt latency
6. ARM9E-S Coprocessor Interface
6.1. About the coprocessor interface
6.1.1. Coprocessor pipeline operates in step with the ARM9E-S
6.1.2. Coprocessor pipeline one cycle behind the ARM9E-S
6.2. LDC/STC
6.2.1. Coprocessor handshake encoding
6.3. MCR/MRC
6.5. Interlocked MCR
6.6. Interlocked MCRR
6.7. CDP
6.8. Privileged instructions
6.9. Busy-waiting and interrupts
6.10. Coprocessor 15 MCRs
6.11. Connecting coprocessors
6.11.1. Connecting a single coprocessor
6.11.2. Connecting multiple coprocessors
6.11.3. No external coprocessor
6.11.4. Undefined instructions
7. Debug Interface and EmbeddedICE-RT
7.1. About the debug interface
7.1.1. Halt mode
7.1.2. Monitor mode
7.2. Debug systems
7.2.1. The debug host
7.2.2. The protocol converter
7.2.3. The ARM9E-S
7.3. About EmbeddedICE-RT
7.4. Disabling EmbeddedICE-RT
7.5. Debug interface signals
7.5.1. Entry into debug state on breakpoint
7.5.2. Breakpoints and exceptions
7.5.3. Watchpoints
7.5.4. Watchpoints and exceptions
7.5.5. Debug request
7.5.6. Actions of the ARM9E-S in debug state
7.6. ARM9E-S core clock domains
7.6.1. Clocks and synchronization
7.7. Determining the core and system state
7.8. The debug communications channel
7.8.1. Debug comms channel registers
7.8.2. Debug comms channel control register
7.8.3. Comms channel monitor mode debug status register
7.8.4. Communications using the comms channel
7.9. Monitor mode debug
8. Instruction Cycle Times
8.1. Instruction cycle count summary
8.2. Introduction to detailed instruction cycle timings
8.3. Branch and ARM branch with link
8.4. Thumb branch with link
8.5. Branch and exchange
8.6. Thumb Branch, Link, and Exchange <immediate>
8.7. Data operations
8.8. MRS
8.9. MSR operations
8.10. Multiply and multiply accumulate
8.10.1. Interlocks
8.11.1. Interlocks
8.12. Load register
8.12.1. Interlocks
8.13. Store register
8.14. Load multiple registers
8.14.1. Interlocks
8.15. Store multiple registers
8.16. Load double register
8.17. Store double register
8.18. Data swap
8.18.1. Interlocks
8.19. PLD
8.20. Software interrupt, undefined instruction, and exception entry
8.21. Coprocessor data processing operation
8.22. Load coprocessor register (from memory)
8.23. Store coprocessor register (to memory)
8.24. Coprocessor register transfer (to ARM)
8.25. Coprocessor register transfer (from ARM)
8.26. Double coprocessor register transfer (to ARM)
8.27. Double coprocessor register transfer (from ARM)
8.28. Coprocessor absent
8.29. Unexecuted instructions
A. Signal Descriptions
A.1. Clock interface signals
A.2. Instruction memory interface signals
A.3. Data memory interface signals
A.4. Miscellaneous signals
A.5. Coprocessor interface signals
A.6. Debug signals
B. AC Parameters
B.1. Timing diagrams
B.2. AC timing parameter definitions
C. Differences Between the ARM9E-S and the ARM9TDMI
C.1. Interface signals
C.2. ATPG scan interface
C.3. Timing parameters
C.4. ARM9E-S design considerations
C.4.1. Master clock
C.4.2. JTAG interface timing
C.4.3. Interrupt timing
C.4.4. Address class signal timing
C.4.5. Data Aborts
C.5. ARM9E-S debugger considerations
D. Debug in depth
D.1. Scan chains and JTAG interface
D.1.1. Debug scan chains
D.1.2. TAP state machine
D.2. Resetting the TAP controller
D.3. Instruction register
D.4. Public instructions
D.4.1. EXTEST (0000)
D.4.2. SAMPLE/PRELOAD (0011)
D.4.3. SCAN_N (0010)
D.4.4. INTEST (1100)
D.4.5. IDCODE (1110)
D.4.6. BYPASS (1111)
D.4.7. RESTART (0100)
D.5. Test data registers
D.5.1. Bypass register
D.5.2. ARM9E-S device identification (ID) code register
D.5.3. Instruction register
D.5.4. Scan path select register
D.5.5. Scan chains 1 and 2
D.6. ARM9E-S core clock domains
D.7. Determining the core and system state
D.7.1. Determining the core state
D.7.2. Determining the system state
D.7.3. Exit from debug state
D.8. Behavior of the program counter during debug
D.8.1. Breakpoints
D.8.2. Watchpoints
D.8.3. Watchpoint with another exception
D.8.4. Watchpoint and breakpoint
D.8.5. Debug request
D.8.6. System speed access
D.8.7. Summary of return address calculations
D.9. Priorities and exceptions
D.9.1. Breakpoint with Prefetch Abort
D.9.2. Interrupts
D.9.3. Data Aborts
D.10. EmbeddedICE-RT logic
D.10.1. Register map
D.10.2. Programming and reading EmbeddedICE-RT logic registers
D.10.3. Using the mask registers
D.10.4. Watchpoint control registers
D.10.5. Debug control register
D.10.6. Debug status register
D.10.7. Vector catch register
D.11. Vector catching
D.12. Single-stepping
D.13. Coupling breakpoints and watchpoints
D.13.1. Breakpoint and watchpoint coupling example
D.13.2. DBGRNG signal
D.14. Disabling EmbeddedICE-RT
D.15. EmbeddedICE-RT timing

List of Figures

1. Key to timing diagram conventions
1.1. Five-stage pipeline
1.2. The instruction pipeline
1.3. ARM9E-S block diagram
1.4. ARM9E-S core diagram
1.5. ARM9E-S interface diagram
2.1. Big-endian addresses of bytes within words
2.2. Little-endian addresses of bytes within words
2.3. Register organization in ARM state
2.4. Register organization in Thumb state
2.5. Mapping of Thumb state registers onto ARM state registers
2.6. Program status register
3.1. Power-on reset
3.2. ARM9E-S behavior on exit from reset
4.1. Simple memory cycle
4.2. Nonsequential instruction fetch cycle
4.3. Sequential instruction fetch cycles
4.4. Merged I-S cycle
4.5. ARM9TDMI effect of DABORT on following memory access
4.6. ARM9E-S aborted data memory access
4.7. Data replication
4.8. Simple memory cycle
4.9. Nonsequential data memory cycle
4.10. Back to back memory cycles
4.11. Sequential access cycles
4.12. Use of CLKEN
4.13. Alteration of next memory request during waited bus cycle
5.1. Retaking the FIQ exception
5.2. Stopping CLK for power saving
5.3. Using CLK and CLKEN for best interrupt latency
6.1. ARM9E-S LDC/STC cycle timing
6.2. ARM9E-S coprocessor clocking
6.3. ARM9E-S MCR or MRC transfer timing
6.4. ARM9E-S MCRR or MRRC transfer timing
6.5. ARM9E-S interlocked MCR
6.6. ARM9E-S interlocked MCRR
6.7. ARM9E-S late-canceled CDP
6.8. ARM9E-S privileged instructions
6.9. ARM9E-S busy waiting and interrupts
6.10. ARM9E-S coprocessor 15 MCRs
6.11. Coprocessor connections
7.1. Typical debug system
7.2. ARM9E-S block diagram
7.3. The ARM9E-S, TAP controller, and EmbeddedICE-RT
7.4. Breakpoint timing
7.5. Watchpoint entry with data processing instruction
7.6. Watchpoint entry with branch
7.7. Clock synchronization
7.8. Debug comms channel control register
7.9. Coprocessor 14 monitor mode debug status register format
B.1. Instruction memory interface timing
B.2. Data memory interface timing
B.3. Clock enable timing
B.4. Coprocessor interface timing
B.5. Exception and configuration timing
B.6. Debug interface timing
B.7. Interrupt sensitivity status timing
B.8. JTAG interface timing
B.9. DBGSDOUT to DBGTDO relationship
D.1. ARM9E-S scan chain arrangements
D.2. Test access port controller state transitions
D.3. ID code register format
D.4. Typical scan chain cell
D.5. Debug exit sequence
D.6. Debug state entry
D.7. ARM9E-S EmbeddedICE macrocell overview
D.8. Watchpoint control register for data comparison
D.9. Watchpoint control register for instruction comparison
D.10. Debug control register format
D.11. Debug status register
D.12. Debug control and status register structure
D.13. Vector catch register

List of Tables

1.1. Key to tables
1.2. ARM instruction set summary
1.3. Addressing mode 2
1.4. Addressing mode 2 (privileged)
1.5. Addressing mode 3
1.6. Addressing mode 4 (load)
1.7. Addressing mode 4 (store)
1.8. Addressing mode 5 (load)
1.9. Oprnd2
1.10. Fields
1.11. Condition fields
1.12. Thumb instruction set summary
2.1. Register mode identifiers
2.2. PSR mode bit values
2.3. Exception entry and exit
2.4. Configuration of exception vector address locations
2.5. Exception vectors
3.1. Reset modes
4.1. Transfer widths
4.2. InTRANS encoding
4.3. Significant address bits
4.4. 32-bit instruction fetches
4.5. Halfword accesses
4.6. Cycle types
4.7. Burst types
4.8. Transfer widths
4.9. DnTRANS encoding
4.10. Transfer size encoding
4.11. Significant address bits
4.12. Word accesses
4.13. Halfword accesses
4.14. Byte accesses
4.15. Cycle types
4.16. Burst types
6.1. Handshake signals
6.2. Handshake signal connections
7.1. Coprocessor 14 register map
8.1. Key to tables
8.2. ARM instruction cycle counts
8.3. Key to cycle timing tables
8.4. Branch and ARM branch with link cycle timings
8.5. Thumb branch with link cycle timing
8.6. Branch and exchange cycle timing
8.7. Thumb branch, link and exchange cycle timing
8.8. Data operation cycle timing
8.9. MRS cycle timing
8.10. MSR cycle timing
8.11. MUL and MLA cycle timing
8.12. MULS and MLAS cycle timing
8.13. SMULL, UMULL, SMLAL, and UMLAL cycle timing
8.14. SMULLS, UMULLS, SMLALS, and UMLALS cycle timing
8.15. SMULxy, SMLAxy, SMULWy, and SMLAWy cycle timing
8.16. SMLALxy cycle timing
8.17. QADD, QDADD, QSUB, and QDSUB cycle timing
8.18. Load register operation cycle timing
8.19. Cycle timing for load operations resulting in interlocks
8.20. Example sequence LDRB, NOP and ADD cycle timing
8.21. Example sequence LDRB and STMIA cycle timing
8.22. Store register operation cycle timing
8.23. LDM cycle timing
8.24. STM cycle timing
8.25. Data swap cycle timing
8.26. PLD operation cycle timing
8.27. Exception entry cycle timing
8.28. Coprocessor data operation cycle timing
8.29. Load coprocessor register cycle timing
8.30. Store coprocessor register cycle timing
8.31. MRC instruction cycle timing
8.32. MCR instruction cycle timing
8.33. MRRC instruction cycle timing
8.34. MCRR instruction cycle timing
8.35. Coprocessor absent instruction cycle timing
8.36. Unexecuted instruction cycle timing
A.1. Clock interface signals
A.2. Instruction memory interface signals
A.3. Data memory interface signals
A.4. Miscellaneous signals
A.5. Coprocessor interface signals
A.6. Debug signals
B.1. Target AC timing parameters
C.1. ARM9E-S signals and ARM9TDMI hard macrocell equivalents
D.1. Public instructions
D.2. Scan chain number allocation
D.3. Scan chain 1 bit order
D.4. ARM9E-S EmbeddedICE-RT logic register map
D.5. Watchpoint control register for data comparison functions
D.6. Watchpoint control register for instruction comparison functions
D.7. Debug control register bit functions
D.8. Interrupt signal control
D.9. Debug status register bit functions

Proprietary Notice

ARM, The ARM Powered logo, Thumb, and StrongARM are registered trademarks of ARM Limited.

The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, PrimeCell, ARM7TDMI, ARM7TDMI-S, ARM9TDMI, ARM9E-S, ARM946E-S, ARM966E-S, ETM7, ETM9, TDMI, and STRONG are trademarks of ARM Limited.

All other products or services mentioned herein may be trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Figure D.2 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2000, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A16th December 1999First release.
Revision B12th September 2000Second release.
Copyright © 1999, 2000 ARM Limited. All rights reserved.. All rights reserved.ARM DDI 0165B