AHB CPU Wrappers Technical Reference Manual 5.2. Signal interface

5.2. Signal interface

This section describes the signal interface of A940TWrap. It does not describe the ARM940T. Only those signals from the ARM940T core that are used by the AHB wrapper are described. All other core signals (for example, coprocessor interface and interrupt inputs) must be connected to the external system in the same way as for an ASB-native design. See the ARM940T Datasheet for the relevant information.

Note

The exception is BCLK, which must be connected directly to the AHB system clock HCLK.

Table 5.1 describes the signals used by the ARM940T AHB wrapper.

Table 5.1. ARM940T AHB signal descriptions

Signal	Direction	Description
System inputs
HCLK	Input	Bus clock. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.
HRESETn	Input	Reset. The bus reset signal is active LOW and is used to reset the system and the bus. This is the only active LOW AHB signal.
Master inputs
HRDATAM[31:0]	Input	Read data bus. Used to transfer data to the ARM940T in master mode.
HREADYM	Input	Transfer done. When HIGH, this signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.
HRESPM[1:0]	Input	Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response.
HGRANTM	Input	Bus grant. This signal indicates that the ARM940T is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADYM is HIGH, so a master gains access to the bus when both HREADYM and HGRANTM are HIGH.
Master outputs
HADDRM[31:0]	Output	This is the 32-bit system address bus.
HTRANSM[1:0]	Output	Transfer type. This signal indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.
HWRITEM	Output	Transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer.
HSIZEM[2:0]	Output	Transfer size. Indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit).
HBURSTM[2:0]	Output	Burst type. Indicates if the transfer forms part of a burst. The ARM940T performs incrementing bursts of type INCR, INCR4, or INCR8.
HPROTM[3:0]	Output	Protection control. These signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a Supervisor mode access or User mode access.
HWDATAM[31:0]	Output	Write data bus. Used to transfer data from the ARM940T in master mode.
HBUSREQM	Output	Bus request. A signal from the wrapper to the bus arbiter which indicates that it requires the bus.
HLOCKM	Output	Locked transfers. When HIGH, this signal indicates that the master requires locked access to the bus and no other master must be granted the bus until this signal is LOW.
Slave inputs
HADDRS[11:2]	Input	This is the 32-bit system address bus.
HTRANS1S	Input	Transfer type. This is attached to bit 1 of the AHB HTRANS[1:0] bus. It indicates an active (NONSEQ or SEQ) or inactive (IDLE or BUSY) transfer.
HWRITES	Input	Transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer.
HWDATAS[31:0]	Input	Write data bus. Used to transfer data to the ARM940T in slave mode.
HSELS	Input	This signal selects the ARM940T as slave.
HREADYS	Input	Transfer done. When HIGH, this signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.
Slave outputs
HRDATAS[31:0]	Output	Read data bus. Used to transfer data from the ARM940T in slave mode.
HREADYOUTS	Output	Transfer done. When HIGH the HREADYOUTS signal indicates that a transfer to the ARM940T has finished. This signal can be driven LOW to extend a transfer.
HRESPS[1:0]	Output	Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response. The ARM940T always responds with OKAY.

Table 5.2 describes the signals to the ARM940T core.

Table 5.2. Signals to ARM940T core

Signal	Direction	Description
Shared master/slave signals
BnRES	Output	Bus reset signal which is active LOW.
BD[31:0]	Input/output	Data bus. For master mode this is connected to HRDATAM and HWDATAM, for test mode it is connected to HRDATAS and HWDATAS.
BWRITE	Input/output	Transfer direction. This is derived from HWRITE. When HIGH this signal indicates a write transfer and when LOW a read transfer. During test this signal is driven by the wrapper.
BERROR	Input/output	Error response. For master mode, this provides the response from the slave (DONE, ERROR, or WAIT). For slave mode, the ARM940T always responds with DONE.
BLAST	Input/output	Last response. For master mode, this provides the response from the slave (DONE, ERROR, or WAIT). For slave mode, the ARM940T always responds with DONE.
BWAIT	Input/output	Wait response. For master mode, this provides the response from the slave (DONE, ERROR, or WAIT). For slave mode, the ARM940T always responds with DONE.
Master inputs
BA[31:0]	Input	This is the ASB address bus for master mode.
AREQ	Input	Bus request. Indicates that the ARM940T is requesting the bus.
BURST[1:0]	Input	Burst type. Contains information regarding the type of access being performed by the core.
BLOK	Input	Locked transfer. The ARM940T requires a locked bus transfer during a SWP instruction.
BPROT[1:0]	Input	Protection control. Indicates whether the current access is for data or opcode, and privileged or user level access.
BSIZE[1:0]	Input	Transfer size. Indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit).
BTRAN[1:0]	Input	Transfer type. Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, or ADDRESS-ONLY.
Master outputs
AGNT	Output	Bus grant. Indicates that the ARM940T has control of the ASB.
Slave outputs
DSEL	Output	Slave select. Select line for accesses to the core during slave mode.

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