4.2. Signal interface

This section describes the signal interface of A920TWrap. It does not describe the ARM920T. Only those signals from the ARM920T core that are used by the AHB wrapper are described. All other core signals (for example, coprocessor interface and interrupt inputs) must be connected to the external system in the same way as for an ASB-native design. See the ARM920T Datasheet for the relevant information.

Note

The exception is BCLK, which must be connected directly to the AHB system clock HCLK.

Table 4.1 describes the signals used by the ARM920T AHB wrapper.

Table 4.1. ARM920T AHB signal descriptions

Signal

Direction

Description

System inputs

HCLK

Input

Bus clock. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.

HRESETn

Input

Reset. The bus reset signal is active LOW and is used to reset the system and the bus. This is the only active LOW AHB signal.

Master inputs

HRDATAM[31:0]

Input

Read data bus. Used to transfer data to the ARM920T in master mode.

HREADYM

Input

Transfer done. When HIGH the HREADYM signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESPM[1:0]

Input

Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response.

HGRANTM

Input

Bus grant. Indicates that the ARM920T is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADYM is HIGH, so a master gains access to the bus when both HREADYM and HGRANTM are HIGH.

Master outputs

HADDRM[31:0]

Output

This is the 32-bit system address bus.

HTRANSM[1:0]

Output

Transfer type. This signal indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

HWRITEM

Output

Transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer.

HSIZEM[2:0]

Output

Transfer size. Indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit).

HBURSTM[2:0]

Output

Burst type. Indicates if the transfer forms part of a burst. The ARM920T performs incrementing bursts of type INCR, INCR4, or INCR8.

HPROTM[3:0]

Output

Protection control. These signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a Supervisor mode access or User mode access.

HWDATAM[31:0]

Output

Write data bus. Used to transfer data from the ARM920T in master mode.

HBUSREQM

Output

Bus request. A signal from the wrapper to the bus arbiter that indicates that it requires the bus.

HLOCKM

Output

Locked transfer. When HIGH, this signal indicates that the master requires locked access to the bus and no other master must be granted the bus until this signal is LOW.

Slave inputs

HADDRS[11:2]

Input

This is the 32-bit system address bus.

HTRANS1S

Input

Transfer type. This is attached to bit 1 of the AHB HTRANS[1:0] bus. It indicates an active (NONSEQ or SEQ) or inactive (IDLE or BUSY) transfer.

HWRITES

Input

Transfer direction. When HIGH, this signal indicates a write transfer and when LOW a read transfer.

HWDATAS[31:0]

Input

Write data bus. Used to transfer data to the ARM920T in slave mode.

HSELS

Input

This signal selects the ARM920T as slave.

HREADYS

Input

Transfer done. When HIGH, this signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

Slave outputs

HRDATAS[31:0]

Output

Read data bus. Used to transfer data from the ARM920T in slave mode.

HREADYOUTS

Output

Transfer done. When HIGH, this signal indicates that a transfer to the ARM920T has finished. This signal can be driven LOW to extend a transfer.

HRESPS[1:0]

Output

Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response. The ARM920T always responds with OKAY.

Table 4.2 describes the signals to the ARM920T core.

Table 4.2. Signals to ARM920T core

Signal

Direction

Description

Shared master/slave signals

BnRES

Output

Bus reset signal which is active LOW.

DIN[31:0]

Output

Data bus. For master mode this is connected to HRDATAM, for test mode it is connected to HWDATAS.

DOUT[31:0]

Input

Data bus. For master mode this is connected to HWDATAM, for test mode it is connected to HRDATAS.

Master inputs

AOUT[31:0]

Input

This is the ASB address bus for master mode.

AREQ

Input

Bus request. Indicates that the ARM920T is requesting the bus.

ASTB

Input

Indicates that a transfer commences on the next cycle.

BURST[1:0]

Input

Burst type. Contains information regarding the type of access being performed by the core.

LOK

Input

Locked transfer. The ARM920T requires a locked bus transfer during a SWP instruction.

NCMAHB

Input

Indicates that there is another transfer in the current burst read from a noncacheable memory area.

PROT[1:0]

Input

Protection control. Indicates whether the current access is for data or opcode, and privileged or user level access.

SIZE[1:0]

Input

Transfer size. Indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit).

TRAN[1:0]

Input

Transfer type. Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, or ADDRESS-ONLY.

WRITEOUT

Input

Transfer direction. Indicates a write access in master mode.

Master outputs

AGNT

Output

Bus grant. Indicates that the ARM920T has control of the ASB.

WAITIN

Output

Wait response. Indicates wait states to the core.

ERRORIN

Output

Error response. Indicates that an error has occurred during the access.

Slave inputs

WAITOUT

Input

Wait response. Indicates wait states during slave mode.

Slave outputs

AIN[11:2]

Output

Slave mode address bus.

DSEL

Output

Select line for accesses to the core during slave mode.

WRITEIN

Output

Transfer direction. Indicates a write access in slave mode.

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