AHB CPU Wrappers Technical Reference Manual 2.2. Signal interface

2.2. Signal interface

The ARM720T AHB wrapper contains both AHB master and AHB slave interfaces. The master interface is used during normal system operation. The slave interface is used during testing of the ARM720T when the Test Interface Controller (TIC) is acting as the current AHB bus master.

This section describes the signal interface of A720TWrap. It does not describe the ARM720T. Only those signals from the ARM720T core that are used by the AHB wrapper are described. All other core signals (for example, coprocessor interface and interrupt inputs) must be connected to the external system in the same way as for an ASB-native design. See the ARM720T Datasheet for the relevant information.

Table 2.1 describes the signals used by the ARM720T AHB wrapper.

Table 2.1. ARM720T AHB signal descriptions

Signal	Direction	Description
System inputs
HCLK	Input	Bus clock. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.
HRESETn	Input	Reset. The bus reset signal is active LOW and is used to reset the system and the bus. This is the only active LOW AHB signal.
Master inputs
HRDATAM[31:0]	Input	Read data bus. Used to transfer data to the ARM720T in master mode.
HREADYM	Input	Transfer done. When HIGH the HREADYM signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.
HRESPM[1:0]	Input	Transfer response. Indicates an OKAY, ERROR, RETRY, or SPLIT response.
HGRANTM	Input	Bus grant. Indicates that the ARM720T is currently the highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADYM is HIGH, so a master gains access to the bus when both HREADYM and HGRANTM are HIGH.
Master outputs
HADDRM[31:0]	Output	This is the 32-bit system address bus.
HTRANSM[1:0]	Output	Transfer type. Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, or IDLE.
HWRITEM	Output	Transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer.
HSIZEM[2:0]	Output	Transfer size. Indicates the size of the transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit).
HBURSTM[2:0]	Output	Burst type. Indicates if the transfer forms part of a burst. The ARM720T only performs incrementing bursts of type INCR.
HPROTM[3:0]	Output	Protection control. These signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a Supervisor mode access or User mode access. This is not supported by the ARM720T wrapper, and is always `0000`.
HWDATAM[31:0]	Output	Write data bus. Used to transfer data from the ARM720T in master mode.
HBUSREQM	Output	Bus request. A signal from the wrapper to the bus arbiter which indicates that it requires the bus.
HLOCKM	Output	Locked transfers. When HIGH this signal indicates that the master requires locked access to the bus and no other master must be granted the bus until this signal is LOW.
Slave inputs
HSELS	Input	This signal selects the ARM720T as slave.
HWRITES	Input	Transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer.
HTRANS1S	Input	Transfer type. This is attached to bit 1 of the AHB HTRANS[1:0] bus. It indicates an active (NONSEQ or SEQ) or inactive (IDLE or BUSY) transfer.
HWDATAS[31:0]	Input	Write data bus. Used to transfer data to the ARM720T in slave mode.
HREADYS	Input	Transfer done. Indicates that the current transfer on the AHB is finished.
Slave outputs
HRDATAS[31:0]	Output	Read data bus. Used to transfer data from the ARM720T in slave mode.
HREADYOUTS	Output	Transfer done. In test mode, this signal indicates when a transfer can complete.
HRESPS[1:0]	Output	Transfer response. Indicates a fixed OKAY response.

Table 2.2 describes the signals to the ARM720T core.

Table 2.2. Signals to ARM720T core

Signal	Direction	Description
BCLK	Output	Bus clock. This times all transfers to and from the ARM720T.
BnRES	Output	Bus reset signal which is active LOW.
BERROR	Output	Error response. Not supported. BERROR is LOW and a fixed OKAY response is supplied.
BLAST	Output	Last response. Not supported. BLAST is LOW and a fixed continue burst response is supplied.
BWAIT	Output	Wait response. Fixed for zero wait state response, BWAIT is LOW. Wait states are controlled by gating BCLK to the ARM720T.
AREQ	Input	Bus request. Indicates the ARM720T is requesting the bus.
BA[31:0]	Input	This is the 32-bit system address bus.
BLOK	Input	Locked transfer. The ARM720T requires a locked bus transfer during a SWP instruction.
BSIZE[1:0]	Input	Transfer size. Indicates the size of the transfer, which is either byte (8-bit), halfword (16-bit) or word (32-bit).
BTRAN[1:0]	Input	Transfer type. Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, or ADDRESS-ONLY.
BWRITE	Input/output	Transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer. During test this signal is driven by the wrapper. During normal operation, it is driven by the ARM720T core.
BD[31:0]	Input/output	Data bus. For master mode write BD is connected to HWDATAM and read BD is connected to HRDATAM. For test mode write BD is connected to HWDATAS and read BD is connected to HRDATAS.
AGNTarm	Output	Bus grant. In test mode this signal degrants the ARM720T the use of the bus. This is set LOW by the test wrapper state machine.
DSEL	Output	Slave select. In test mode this signal selects the ARM720T as slave. This is set HIGH by the test wrapper state machine.

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