2.3.4. A7x0TWrapTest

This block handles all the bus interface requirements when the ARM720T is operating in test mode. Its main functions are to ensure a clean entry and exit from the test mode, and to maintain synchronization between the TIC interface and the embedded test mode state machine within the ARM720T.

There are two main sections to this block:

Test state machine

A test state machine is used as the central controller to provide control of the AHB bus for all test mode transaction types.

Figure 2.3 shows the test state machine.

Figure 2.3. Test state machine

There are ten states in the test state machine:

ST_MASTER_MODE

This is the IDLE state for the test state machine. During this state the ARM720T is acting as a bus master and the test logic is disabled. This state is exited when the first transfer of a test sequence is detected.

ST_ENTER_TEST_1

This is the first state on the entry into test and during this state the AGNTarm signal is removed from the ARM720T.

ST_ENTER_TEST_2

During the second state on entry in to test the ARM720T clock is enabled so that the ARM720T becomes degranted and tristates all the output signals that must become inputs for test.

ST_ENTER_TEST_3

During the third state on entry in to test the BWRITE signal to the ARM720T becomes driven from the test wrapper.

ST_TEST_MODE_WRITE

This state is entered whenever a WRITE transfer to the ARM720T is being performed. During this state the HWDATAS is driven on to the bidirectional data bus (BD) of the ARM720T.

ST_TEST_MODE_READ

In this state a READ transfer from the ARM720T occurs. During this state the bidirectional data bus (BD) of the ARM720T is driven on to HRDATAS.

ST_TEST_MODE_IDLE_1

This state is the first of two IDLE states that occur when the ARM720T is moving between READ and WRITE transfers.

ST_TEST_MODE_IDLE_2

This state is the second of two IDLE states that occur when the ARM720T is moving between READ and WRITE transfers. If this state is followed by another IDLE transfer then this indicates the end of the test process and the next state will be ST_EXIT_TEST_1, otherwise this state is followed by a READ or WRITE transfer.

ST_EXIT_TEST_1

In the first exit from test state, the signals that are driven from the wrapper during test become tristate.

ST_EXIT_TEST_2

In the second exit from test state, the ARM720T is regranted as a bus master by driving AGNTarm HIGH. After this state the ARM720T returns to the ST_MASTER_MODE state which indicates that the ARM720T has returned to normal operation.

Test logic output

The output signals generated from the test state machine are:

AGNTarm

This signal is driven LOW throughout the test process to degrant the ARM720T so that it can be tested as a slave.

TestEnable

This signal is used to clock the core throughout the test process. The ARM720T is always clocked except in the ST_TEST_MODE_IDLE_2 state.

SelArmTest

The tristate control of signals, such as BWAIT, BERROR, and BLAST is controlled by the SelArmTest signal. This ensures that the wrapper does not drive these signals during test when the ARM720T is driving them to respond to slave transfers.

DSEL

The DSEL select signal to the core is generated from the test state machine before the ST_TEST_MODE_READ or ST_TEST_MODE_WRITE states. A transparent latch is used in the generation of the DSEL signal to allow for designs that have late HTRANSS timing. In low speed designs it is possible to replace this latch with a falling edge register.

BWRITE

The write signal to the ARM720T is generated from the HWRITES signal and is a tristate signal which is only driven during test. The write signal must be timed with reference to the rising edge of BCLK and therefore a falling edge HCLK register must be used to generate this signal.

BD

The bidirectional data bus to the ARM720T is driven with the write data, HWDATAS, during write transfers to the ARM720T.

HREADYOUTS

The HREADYOUTS signal is used to insert wait states on the bus during transfers to the test wrapper. Wait states are only required during the entry in to test and at all other times during the test process transfers receive a zero wait state OKAY response.

HRESPS

The response signals are fixed to provide an OKAY response.

HRDATAS

During test read transfers the data from BD must be driven on to HRDATAS. At all other times this bus is driven LOW to prevent unnecessary toggling.

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