4.3.3. A920TWrapSM

In master mode, this block converts the ASB accesses from the core into pseudo-AHB accesses. This pseudo-AHB format is similar to AHB-Lite. The following sections of the code are explained:

Special signals

Two signals exist on the ARM920T to improve the performance of the AHB wrapper:


Indicates when there is another access (after the current one) in a burst of reads to a noncacheable region. Allows the AHB address phase of the next read to commence before the access commences on the ASB, by use of a local address incrementer.


Indicates that the current IDLE cycle on the ASB is the first part of a merged I-S cycle, That is, the control information contained within the IDLE cycle is correct for the following SEQ cycle, and so the access can, in some cases, commence on the AHB in advance.

Main state machine

The main state machine uses the state variable AddrState (which is registered to create LastAddrState). This can take the following enumerated values:


Default state. Indicates that no transfer is taking place on the AHB.


First cycle of read transfer. A NONSEQ access is indicated on HTRANS.


Indicates that the first cycle of a read transfer has been waited. A NONSEQ access is indicated on HTRANS.


Indicates sequential transfers in a burst of reads. A SEQ transfer is indicated on HTRANS.


Start of SWP instruction. This state stalls the core to allow HLOCK to be asserted for one cycle before commencing the read transaction. An IDLE cycle is indicated on HTRANS.


A wait is indicated on the ASB but cannot yet commence on the AHB. An IDLE cycle is indicated on HTRANS.


First cycle of a nonbuffered write transfer. A NONSEQ access is indicated on HTRANS.


Synchronization state to allow the response to the previous write transfer to propagate to the core before commencing the next transfer. A BUSY transfer is indicated on HTRANS when more writes are likely to follow, else IDLE.


Indicates sequential transfers in a burst of nonbuffered writes. A SEQ transfer is indicated on HTRANS.


First cycle of a buffered write transfer. A NONSEQ access is indicated on HTRANS.


Indicates sequential transfers in a burst of buffered writes. A SEQ transfer is indicated on HTRANS.

Figure 4.2 shows the possible state transitions. State transitions occur on the rising edge of HCLK. Transitions back to the same state can occur either when the access on the pseudo-AHB is waited, or during sequential accesses in a burst (BUF_WRITE_SEQ and READ_SEQ only). Those states which cannot transition back to themselves (WRITE_ASTB, READ_START, LOCK_STALL) provide a single cycle to allow synchronization between events on the ASB and the AHB.

Figure 4.2. ARM920T AHB wrapper main state machine

Address generation

There are three internal sources of address:

  • direct from the ARM920T core

  • a registered version of the core address

  • a locally incremented address created within A920TWrapSM.

The direct address is used when the core access and the AHB access occur in the same clock cycle. The registered version of the core address is used when the AHB access is waited, but the core has been allowed to step on to determine the next access to be performed. The locally incremented address is used when the AHB access commences before the core access (for example, when the NCMAHB signal indicates more accesses in the current burst of reads).

Wait states

The inclusion of the NCMAHB and ASTB signals has enabled the ARM920T AHB wrapper to be designed in such a way that a minimum number of extra wait states are added by the conversion from ASB to AHB. Wait states on the AHB (indicated by HREADY being LOW) are propagated to the ARM920T only when the core is attempting to access the bus. Because of this, a string of IDLE cycles on the ASB is not waited. Additional wait states (where one wait state equates to a single cycle of HCLK) are added as follows:

  • +1 wait state on each nonbuffered write (either a single access, or each beat in a burst). This allows for the AHB ERROR response to propagate back to the ASB.

  • +1 wait state on the read at the start of a SWP instruction. This allows for HLOCK to be asserted for a cycle before the AHB access commences.

Error support

The ARM920T AHB wrapper includes support for the ERROR response on HRESP. The ERROR response is only valid for the following accesses:

  • read and write accesses to NCNB address regions

  • read accesses to NCB address regions.

For all other access types, the ERROR response is blanked within the AHB wrapper. This is because, due to the pipelining within the AHB wrapper, an error response to certain CB accesses would otherwise appear on the ASB in response to the next access.


Page table walks are a special case, and ERROR response is not supported for these accesses (either by the ARM920T core, or by the AHB wrapper).

Control signaling (HTRANS, HSIZE, HBURST, HPROT)

Table 4.3 shows the control signal values used by the ARM920T AHB wrapper.

Table 4.3. Control signal values




00: IDLE

01: BUSY




00: BYTE


10: WORD


001: INCR

011: INCR4

101: INCR8


bit 3: 1 = cacheable, 0 = not cacheable (only valid for reads, 0 for all writes)

bit 2: 1 = bufferable, 0 = not bufferable (only valid for writes, 0 for all reads)

bit 1: 1 = privileged access, 0 = user access

bit 0: 1 = data access, 0 = opcode fetch.


The cached status of page table walks cannot be correctly determined outside of the core, and HPROT[3] is set to 1 for these accesses.

Copyright © 2001, 2003 ARM Limited. All rights reserved.ARM DDI 0169D