A clock inverter is instantiated within A7x0TWrap (instance name uClockInv) to provide nHCLK (inverted HCLK). This signal is used in the following places:

An inverted version of the clock is used so that all HDL code describes only rising-edge sequential logic. This is done because some cell libraries do not contain falling-edge registers, and also to avoid possible insertion of unwanted clock gating during synthesis.

A clock NAND gate is used within A7x0TWrapMaster (instance name uClockNand) to create BCLK, the bus clock for the ASB interface of the ARM720T.

The clock gates are described in the design block ClockInv and ClockNand. The methodology chosen within the supplied synthesis scripts synthesizes these blocks first, sets them as dont_touch, and then links them in when synthesizing the wrapper. This ensures that the clock gate instances have known references, and also prevents the optimization routines during later synthesis from altering the gates.